📄 main.lss
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///////////////////////////////////////////////////////////////////////////
// Init PMC Step 2.
// Set PLL to 96MHz (96,109MHz) and UDP Clock to 48MHz
// PLL Startup time depends on PLL RC filter: worst case is choosen
// UDP Clock (48,058MHz) is compliant with the Universal Serial Bus
// Specification (+/- 0.25% for full speed)
///////////////////////////////////////////////////////////////////////////
AT91C_BASE_PMC->PMC_PLLR = AT91C_CKGR_USBDIV_1 |
100148: 4b1c ldr r3, [pc, #112] (1001bc <.text+0x1bc>)
10014a: 62cb str r3, [r1, #44]
10014c: 491a ldr r1, [pc, #104] (1001b8 <.text+0x1b8>)
10014e: 2204 movs r2, #4
(16 << 8) |
(AT91C_CKGR_MUL & (72 << 16)) |
(AT91C_CKGR_DIV & 14);
// Wait for PLL stabilization
while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) );
100150: 6e8b ldr r3, [r1, #104]
100152: 4213 tst r3, r2
100154: d0fc beq.n 100150 <AT91F_LowLevelInit+0x20>
100156: 4918 ldr r1, [pc, #96] (1001b8 <.text+0x1b8>)
100158: 2208 movs r2, #8
// Wait until the master clock is established for the case we already
// turn on the PLL
while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
10015a: 6e8b ldr r3, [r1, #104]
10015c: 4213 tst r3, r2
10015e: d0fc beq.n 10015a <AT91F_LowLevelInit+0x2a>
///////////////////////////////////////////////////////////////////////////
// Init PMC Step 3.
// Selection of Master Clock MCK equal to (Processor Clock PCK) PLL/2=48MHz
// The PMC_MCKR register must not be programmed in a single write operation
// (see. Product Errata Sheet)
///////////////////////////////////////////////////////////////////////////
AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
100160: 2304 movs r3, #4
100162: 630b str r3, [r1, #48]
100164: 4914 ldr r1, [pc, #80] (1001b8 <.text+0x1b8>)
100166: 2208 movs r2, #8
// Wait until the master clock is established
while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
100168: 6e8b ldr r3, [r1, #104]
10016a: 4213 tst r3, r2
10016c: d0fc beq.n 100168 <AT91F_LowLevelInit+0x38>
AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
10016e: 6b0b ldr r3, [r1, #48]
100170: 2203 movs r2, #3
100172: 4313 orrs r3, r2
100174: 630b str r3, [r1, #48]
100176: 4910 ldr r1, [pc, #64] (1001b8 <.text+0x1b8>)
100178: 2208 movs r2, #8
// Wait until the master clock is established
while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
10017a: 6e8b ldr r3, [r1, #104]
10017c: 4213 tst r3, r2
10017e: d0fc beq.n 10017a <AT91F_LowLevelInit+0x4a>
///////////////////////////////////////////////////////////////////////////
// Disable Watchdog (write once register)
///////////////////////////////////////////////////////////////////////////
AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
100180: 2380 movs r3, #128
100182: 021b lsls r3, r3, #8
100184: 4a0e ldr r2, [pc, #56] (1001c0 <.text+0x1c0>)
100186: 6053 str r3, [r2, #4]
///////////////////////////////////////////////////////////////////////////
// Init AIC: assign corresponding handler for each interrupt source
///////////////////////////////////////////////////////////////////////////
AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
100188: 490e ldr r1, [pc, #56] (1001c4 <.text+0x1c4>)
10018a: 4a0f ldr r2, [pc, #60] (1001c8 <.text+0x1c8>)
10018c: 2380 movs r3, #128
10018e: 50d1 str r1, [r2, r3]
100190: 2201 movs r2, #1
100192: 490e ldr r1, [pc, #56] (1001cc <.text+0x1cc>)
for (i = 1; i < 31; i++) {
AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
100194: 0093 lsls r3, r2, #2
100196: 480e ldr r0, [pc, #56] (1001d0 <.text+0x1d0>)
100198: 181b adds r3, r3, r0
10019a: 6019 str r1, [r3, #0]
10019c: 3201 adds r2, #1
10019e: 2a1f cmp r2, #31
1001a0: d1f8 bne.n 100194 <AT91F_LowLevelInit+0x64>
}
AT91C_BASE_AIC->AIC_SPU = (unsigned int) AT91F_Spurious_handler;
1001a2: 4b0c ldr r3, [pc, #48] (1001d4 <.text+0x1d4>)
1001a4: 229a movs r2, #154
1001a6: 0052 lsls r2, r2, #1
1001a8: 4907 ldr r1, [pc, #28] (1001c8 <.text+0x1c8>)
1001aa: 508b str r3, [r1, r2]
}
1001ac: 4770 bx lr
1001ae: 0000 lsls r0, r0, #0
1001b0: ff00 ffff undefined
1001b4: 4001 ands r1, r0
1001b6: 0000 lsls r0, r0, #0
1001b8: fc00 ffff stc2 15, cr15, [r0], {255}
1001bc: 100e asrs r6, r1, #32
1001be: 1048 asrs r0, r1, #1
1001c0: fd40 ffff stc2l 15, cr15, [r0, #-1020]
1001c4: 00b8 lsls r0, r7, #2
1001c6: 0020 lsls r0, r4, #0
1001c8: f000 ffff bl 1011ca <__ctors_end__+0x682>
1001cc: 00bc lsls r4, r7, #2
1001ce: 0020 lsls r0, r4, #0
1001d0: f080 ffff bl 1811d2 <__ctors_end__+0x8068a>
1001d4: 00c0 lsls r0, r0, #3
1001d6: 0020 lsls r0, r4, #0
001001d8 <SWI_Handler_User>:
res = 0;
return res;
}
1001d8: 2000 movs r0, #0
1001da: 4770 bx lr
001001dc <AT91F_USB_Open>:
//* \fn AT91F_USB_Open
//* \brief This function Open the USB device
//*----------------------------------------------------------------------------
void AT91F_USB_Open(void)
{
1001dc: b500 push {lr}
// Set the PLL USB Divider
AT91C_BASE_CKGR->CKGR_PLLR |= AT91C_CKGR_USBDIV_1 ;
1001de: 490b ldr r1, [pc, #44] (10020c <.text+0x20c>)
1001e0: 68ca ldr r2, [r1, #12]
1001e2: 2380 movs r3, #128
1001e4: 055b lsls r3, r3, #21
1001e6: 431a orrs r2, r3
1001e8: 60ca str r2, [r1, #12]
// Specific Chip USB Initialisation
// Enables the 48MHz USB clock UDPCK and System Peripheral USB Clock
AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_UDP;
1001ea: 4a09 ldr r2, [pc, #36] (100210 <.text+0x210>)
1001ec: 2380 movs r3, #128
1001ee: 6013 str r3, [r2, #0]
AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_UDP);
1001f0: 011b lsls r3, r3, #4
1001f2: 6113 str r3, [r2, #16]
__inline void AT91F_PIO_CfgOutput(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int pioEnable) // \arg PIO to be enabled
{
pPio->PIO_PER = pioEnable; // Set in PIO mode
1001f4: 4a07 ldr r2, [pc, #28] (100214 <.text+0x214>)
1001f6: 2380 movs r3, #128
1001f8: 025b lsls r3, r3, #9
1001fa: 6013 str r3, [r2, #0]
pPio->PIO_OER = pioEnable; // Configure in Output
1001fc: 6113 str r3, [r2, #16]
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_CfgInput
//* \brief Enable PIO in input mode
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_CfgInput(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int inputEnable) // \arg PIO to be enabled
{
// Disable output
pPio->PIO_ODR = inputEnable;
pPio->PIO_PER = inputEnable;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_CfgOpendrain
//* \brief Configure PIO in open drain
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_CfgOpendrain(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int multiDrvEnable) // \arg pio to be configured in open drain
{
// Configure the multi-drive option
pPio->PIO_MDDR = ~multiDrvEnable;
pPio->PIO_MDER = multiDrvEnable;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_CfgPullup
//* \brief Enable pullup on PIO
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_CfgPullup(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int pullupEnable) // \arg enable pullup on PIO
{
// Connect or not Pullup
pPio->PIO_PPUDR = ~pullupEnable;
pPio->PIO_PPUER = pullupEnable;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_CfgDirectDrive
//* \brief Enable direct drive on PIO
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_CfgDirectDrive(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int directDrive) // \arg PIO to be configured with direct drive
{
// Configure the Direct Drive
pPio->PIO_OWDR = ~directDrive;
pPio->PIO_OWER = directDrive;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_CfgInputFilter
//* \brief Enable input filter on input PIO
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_CfgInputFilter(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int inputFilter) // \arg PIO to be configured with input filter
{
// Configure the Direct Drive
pPio->PIO_IFDR = ~inputFilter;
pPio->PIO_IFER = inputFilter;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_GetInput
//* \brief Return PIO input value
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_PIO_GetInput( // \return PIO input
AT91PS_PIO pPio) // \arg pointer to a PIO controller
{
return pPio->PIO_PDSR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_IsInputSet
//* \brief Test if PIO is input flag is active
//*----------------------------------------------------------------------------
__inline int AT91F_PIO_IsInputSet(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg flag to be tested
{
return (AT91F_PIO_GetInput(pPio) & flag);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_SetOutput
//* \brief Set to 1 output PIO
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_SetOutput(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg output to be set
{
pPio->PIO_SODR = flag;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_ClearOutput
//* \brief Set to 0 output PIO
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_ClearOutput(
AT91PS_PIO pPio, // \arg pointer to a PIO controller
unsigned int flag) // \arg output to be cleared
{
pPio->PIO_CODR = flag;
1001fe: 6353 str r3, [r2, #52]
// Enable UDP PullUp (USB_DP_PUP) : enable & Clear of the corresponding PIO
// Set in PIO mode and Configure in Output
AT91F_PIO_CfgOutput(AT91C_BASE_PIOA,AT91C_PIO_PA16);
// Clear for set the Pul up resistor
AT91F_PIO_ClearOutput(AT91C_BASE_PIOA,AT91C_PIO_PA16);
// CDC Open by structure initialization
AT91F_CDC_Open(&pCDC, AT91C_BASE_UDP);
100200: 4805 ldr r0, [pc, #20] (100218 <.text+0x218>)
100202: 4906 ldr r1, [pc, #24] (10021c <.text+0x21c>)
100204: f000 f874 bl 1002f0 <AT91F_CDC_Open>
}
100208: bc01 pop {r0}
10020a: 4700 bx r0
10020c: fc20 ffff stc2 15, cr15, [r0], #-1020
100210: fc00 ffff stc2 15, cr15, [r0], {255}
100214: f400 ffff bl ffd01216 <__TOP_STACK+0xffaf1216>
100218: 029c lsls r4, r3, #10
10021a: 0020 lsls r0, r4, #0
10021c: 0000 lsls r0, r0, #0
10021e: fffb b5f0 vsli.64 <illegal reg q13.5>, q8, #59
00100220 <main>:
//*--------------------------------------------------------------------------------------
//* Function Name : main
//* Object :
//*--------------------------------------------------------------------------------------
int main ( void )
{
100220: b5f0 push {r4, r5, r6, r7, lr}
100222: 4647 mov r7, r8
100224: b480 push {r7}
100226: b099 sub sp, #100
char data[MSG_SIZE];
unsigned int length;
unsigned int mLen;
unsigned int mTmpLen;
// Enable User Reset and set its minimal assertion to 960 us
AT91C_BASE_RSTC->RSTC_RMR = AT91C_RSTC_URSTEN | (0x4<<8) | (unsigned int)(0xA5<<24);
100228: 4a2b ldr r2, [pc, #172] (1002d8 <.text+0x2d8>)
10022a: 4b2c ldr r3, [pc, #176] (1002dc <.text+0x2dc>)
10022c: 609a str r2, [r3, #8]
__inline void AT91F_PMC_EnablePeriphClock (
AT91PS_PMC pPMC, // \arg pointer to PMC controller
unsigned int periphIds) // \arg IDs of peripherals
{
pPMC->PMC_PCER = periphIds;
10022e: 2204 movs r2, #4
100230: 4b2b ldr r3, [pc, #172] (1002e0 <.text+0x2e0>)
100232: 611a str r2, [r3, #16]
100234: 4a2b ldr r2, [pc, #172] (1002e4 <.text+0x2e4>)
100236: 230f movs r3, #15
100238: 6013 str r3, [r2, #0]
10023a: 6113 str r3, [r2, #16]
10023c: 6313 str r3, [r2, #48]
10023e: 2301 movs r3, #1
100240: 6353 str r3, [r2, #52]
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