📄 prg24_x1.lst
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A 192 fe9d 3011! SUB B2_4 ;Subtract end addr.
A 193 fe9e e304 BCND DONE, GT ;If >0 then done.
fe9f fea3+
A 194 ********Else, goto next row. *
A 195 fea0 691d! LACL FL_ADRS
A 196 fea1 7980 B NEWROW ;Start new row.
fea2 fe6d+
A 197 ;DONE ;(DAF)
A 198 ; RET
TMS320C1x/C2x/C2xx/C5x COFF Assembler Beta Version 6.63 Tue Nov 30 13:52:44 1999
Copyright (c) 1987-1996 Texas Instruments Incorporated
PRG24_X1.ABS PAGE 5
A 199
A 200 ;FINISHED
A 201
A 202 fea3 7a80 DONE CALL ARRAY ;ACCES FLASH IN ARRAY MODE.
fea4 fef3+
A 203 ;DONE IN DUMMY, F24X_ACCS ;Set Array mode (DAF)
A 204 fea5 ef00 RET
A 205
A 206 ;-------------------------------------------------
A 207 ;Programs Hi or Lo byte depending on the BYTE_MASK
A 208 ;-------------------------------------------------
A 209 fea6 PRG_BYTE:
A 210 fea6 7a80 CALL SET_RD_VER0 ;Read word at VER0 level.
fea7 fed6+
A 211 fea8 8b8b MAR *,AR3 ;ARP -> buffer addr index.
A 212 fea9 6980 LACL * ;Get word to program.
A 213 feaa 6c1e! XOR FL_DATA ;Xor with read-back value.
A 214 feab 6e0c! AND BYTE_MASK ;Mask off appropriate byte
A 215 feac e388 BCND PB_END,EQ ;If zero then done.
fead feb5+
A 216 feae bfd0 XOR #0FFFFh ;else, mask off good bits.
feaf ffff
A 217 feb0 901e! SACL FL_DATA ;New data.
A 218 feb1 7a80 CALL EXE_PGM ;PGM Pulse.
feb2 febb+
A 219 feb3 ae0d! SPLK #0,B2_0 ;Set row done flag = 0(False).
feb4 0000
A 220 feb5 ef00 PB_END RET
A 221
A 222
A 223 ************************************************
A 224 * ADJ_ROW: This routine is used to adjust the *
A 225 * row length, if the start or end address of *
A 226 * code being programed does not fall on a row *
A 227 * boundary. The row length is passed in the *
A 228 * B2_2 variable, and the adjustment value to *
A 229 * be subtracted is passed in the accumulator. *
A 230 ************************************************
A 231 feb6 ADJ_ROW
A 232 feb6 be01 CMPL ;Take ones complement.
A 233 feb7 b801 ADD #1 ;Take twos complement.
A 234 feb8 200f! ADD B2_2 ;Add row length.
A 235 feb9 900f! SACL B2_2 ;Save new row length.
A 236 feba ef00 RET
A 237
A 238 ;***********************************************
A 239 ; SET_MODULE: This routine is used to point to *
A 240 ; the appropriate flash array control register.*
A 241 ; The variable FL_ST is returned with the *
A 242 ; correct register address. *
A 243 ; The following temporary resources are used: *
A 244 ; AR0 - Used for comparisons. *
A 245 ; AR4 - Used for flash address. *
A 246 ;***********************************************
TMS320C1x/C2x/C2xx/C5x COFF Assembler Beta Version 6.63 Tue Nov 30 13:52:44 1999
Copyright (c) 1987-1996 Texas Instruments Incorporated
PRG24_X1.ABS PAGE 6
A 247 ;SET_MODULE (DAF)
A 248 ; LAR AR4,FL_ADRS ;AR4 = current address.
A 249 ; SPLK #0,FL_ST ;FL_ST = FLASH0 CTRL REGS
A 250 ; LAR AR0,#4000H ;AR0 = compare value.
A 251 ; CMPR 1 ;If AR4 < AR0 then
A 252 ; ;FL_ADRS < 4000H; SET TC
A 253 ; BCND FL0,TC ;Address is in FL0.
A 254 ; ;Else address is in FL1.
A 255 ; SPLK #04000h,FL_ST ;FL_ST = FLASH1 CTRL REGS
A 256 ;FL0 RET
A 257
A 258
A 259
A 260 ************************************************************
A 261 * THIS SECTION PROGRAMS THE VALUE STORED IN FL_DATA INTO *
A 262 * THE FLASH ADDRESS DEFINED BY FL_ADRS. *
A 263 * *
A 264 * The following resources are used for temporary storage: *
A 265 * AR6 - Parameter passed to Delay. *
A 266 * SPAD1 - Flash program and STOP commands. *
A 267 * SPAD2 - Flash program + EXE command. *
A 268 ************************************************************
A 269 febb EXE_PGM ; *
A 270 * *
A 271 ; IN DUMMY, F24X_ACCS ;Set Array mode
A 272 febb 7a80 CALL ARRAY ;ACCESS ARRAY (DAF) *
febc fef3+
A 273
A 274
A 275 * LOAD WADRS AND WDATA **
A 276 febd 691d! LACL FL_ADRS ;ACC => PROGRAM ADRS *
A 277 febe a71e! TBLW FL_DATA ;LOAD WADRS AND WDATA *
A 278
A 279
A 280 ; OUT DUMMY, F24X_ACCS ;Set Reg mode
A 281 febf 7a80 CALL REGS ;ACCESS FLASH REGS (DAF) *
fec0 fef6+
A 282 * SET-UP WRITE COMMAND WORDS **
A 283 fec1 691c! LACL PROTECT ;GET SEGMENT PROTECT MASK **
A 284 fec2 bfc0 OR #WR_CMND ;OR IN WRITE COMMAND **
fec3 0004
A 285 fec4 9014! SACL SPAD1 ;SPAD1 = WRITE COMMAND **
A 286 fec5 bfc0 OR #WR_EXE ;OR IN EXEBIN COMMAND **
fec6 0045
A 287 fec7 9015! SACL SPAD2 ;SPAD2 = WRITE EXE COMMAND**
A 288 fec8 6921! LACL FL_ST ;ACC => (FLASH) *
A 289 * *
A 290 * ACTIVATE WRITE BIT **
A 291 fec9 a714! TBLW SPAD1 ;EXECUTE COMMAND **
A 292 ; LAR AR6,#D10 ;SET DELAY (DAF) **
A 293 ; CALL DELAY,*,AR6 ;WAIT **
A 294 feca 0b17! RPT DLY10 ;
A 295 fecb 8b00 NOP
A 296 * SET EXEBIN BIT ***
TMS320C1x/C2x/C2xx/C5x COFF Assembler Beta Version 6.63 Tue Nov 30 13:52:44 1999
Copyright (c) 1987-1996 Texas Instruments Incorporated
PRG24_X1.ABS PAGE 7
A 297 fecc a715! TBLW SPAD2 ;EXECUTE COMMAND ***
A 298 ; LAR AR6,#D100 ;SET DELAY (DAF) ***
A 299 ; CALL DELAY,*,AR6 ;WAIT ***
A 300 fecd 0b18! RPT DLY100 ;
A 301 fece 8b00 NOP
A 302 * STOP WRITE OPERATION *
A 303 fecf ae14! SPLK #0,SPAD1 ;SHUTDOWN WRITE OPERATION *
fed0 0000
A 304 fed1 a714! TBLW SPAD1 ;EXECUTE COMMAND *
A 305 fed2 a714! TBLW SPAD1 ;EXECUTE COMMAND *
A 306 ; LAR AR6,#D10 ;SET DELAY (DAF) *
A 307 ; CALL DELAY,*,AR6 ;WAIT *
A 308 fed3 0b17! RPT DLY10 ;
A 309 fed4 8b00 NOP
A 310 fed5 ef00 RET ;RETURN TO CALLING SEQUENCE *
A 311 ************************************************************
A 312
A 313 ***********************************************************
A 314 * ACTIVATE VER0 ON FLASH READS *
A 315 * LOADS FLASH WORD AT ADDR FL_ADRS TO FL_DATA. *
A 316 * Uses SPAD1 for temporary storage of flash comands. *
A 317 ***********************************************************
A 318 fed6 SET_RD_VER0 ;
A 319
A 320 fed6 7a80 CALL REGS ;ACCESS FLASH REGISTERS (DAF)
fed7 fef6+
A 321 ; OUT DUMMY, F24X_ACCS ;Set Reg mode
A 322 fed8 6921! LACL FL_ST ;ACC => FLASH
A 323 fed9 ae14! SPLK #VER0,SPAD1 ;ACTIVATE VER0
feda 0010
A 324 fedb a714! TBLW SPAD1 ;EXECUTE COMMAND
A 325 ; LAR AR6,#D10 ;SET DELAY (DAF)
A 326 ; CALL DELAY,*,AR6 ;WAIT
A 327 fedc 0b17! RPT DLY10 ;
A 328 fedd 8b00 NOP
A 329
A 330 fede 7a80 CALL ARRAY ;ACCESS FLASH ARRAY (DAF)
fedf fef3+
A 331 ; IN DUMMY, F24X_ACCS ;Set Array mode
A 332
A 333 fee0 691d! LACL FL_ADRS ;POINT TO ADRS
A 334 fee1 a61e! TBLR FL_DATA ;GET FLASH WORD 1x read
A 335 fee2 a61e! TBLR FL_DATA ; 2x read
A 336 fee3 a61e! TBLR FL_DATA ; 3x read
A 337
A 338 ; OUT DUMMY, F24X_ACCS ;Set Reg mode
A 339 fee4 7a80 CALL REGS ;ACCESS FLASH REGISTERS
fee5 fef6+
A 340
A 341 fee6 6921! LACL FL_ST ;ACC => FLASH
A 342 fee7 ae14! SPLK #STOP,SPAD1 ;DEACTIVATE VER0
fee8 0000
A 343 fee9 a714! TBLW SPAD1 ;EXECUTE COMMAND
A 344 ; LAR AR6,#D10 ;SET DELAY (DAF)
TMS320C1x/C2x/C2xx/C5x COFF Assembler Beta Version 6.63 Tue Nov 30 13:52:44 1999
Copyright (c) 1987-1996 Texas Instruments Incorporated
PRG24_X1.ABS PAGE 8
A 345 ; CALL DELAY,*,AR6 ;WAIT
A 346 feea 0b17! RPT DLY10 ;
A 347 feeb 8b00 NOP
A 348 feec 7a80 CALL ARRAY ;ACCESS FLASH ARRAY (DAF)
feed fef3+
A 349 ; IN DUMMY, F24X_ACCS ;Set Array mode
A 350 feee ef00 RET ;RETURN TO CALLING SEQUENCE
A 351 ***********************************************************
A 352
A 353
A 354
A 355 ********If here then unit failed to program. *
A 356 feef ae1f! EXIT SPLK #1,ERROR ;Update error flag.
fef0 0001
A 357 ; B FINISHED ;Get outa here.
A 358 fef1 7980 B DONE ;Get outa here. (DAF)
fef2 fea3+
A 359
A 360 fef3 af16! ARRAY: IN DUMMY, F24X_ACCS
fef4 ff0f
A 361
A 362 ; LDP #0E0H
A 363 ; SPLK #0,7018H
A 364 ; LDP #6
A 365 fef5 ef00 RET
A 366
A 367 fef6 0c16! REGS: OUT DUMMY, F24X_ACCS
fef7 ff0f
A 368 ; LDP #0E0H
A 369 ; SPLK #0800H,7018H
A 370 ; LDP #6
A 371 fef8 ef00 RET
A 372
A 373
A 374 .end
No Errors, No Warnings
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