📄 prg24_x1.lst
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C:\DSPTOOLS\FIX_663\DSPA.EXE -a PRG24_X1.ABS -v2xx
TMS320C1x/C2x/C2xx/C5x COFF Assembler Beta Version 6.63 Tue Nov 30 13:52:44 1999
Copyright (c) 1987-1996 Texas Instruments Incorporated
PRG24_X1.ABS PAGE 1
47 3800 .text
48 .copy "PRG24_X1.ASM"
A 1 ;************************************************************
A 2 ;* PROGRAM Subroutine **
A 3 ; **
A 4 ; TMS320F2XX Flash Utilities. **
A 5 ; **
A 6 ; Filename: PRG24_X1.ASM **
A 7 ; Changes: Re-written to include latest flash algorithms. **
A 8 ; **
A 9 ; DSP Applications **
A 10 ; Texas Instruments Inc. **
A 11 ; **
A 12 ; 03 Nov 97 - Optimised code to strip out approx 30 **
A 13 ; words to enable this algorithm to share **
A 14 ; 256 words in B0 together with the F240 **
A 15 ; Serial Boot loader Comms kernel + **
A 16 ; sequencer s/w. **
A 17 ; 11/30/1999 **
A 18 ;Changes20b: Changed conditional branch on line 194 near **
A 19 ; row-done label from GEQ to GT, to prevent **
A 20 ; skipping of last address on sections that end **
A 21 ; with a mult of 32d address (020h,040h,etc.) **
A 22 ; **
A 23 ; Called by : c2xx_bpx.asm or flash application programs. **
A 24 ; **
A 25 ; !!CAUTION - INITIALIZE DP BEFORE CALLING THIS ROUTINE!! **
A 26 ; **
A 27 ; Function : This routine programs all or part of the **
A 28 ; flash as specified by the variables: **
A 29 ; PRG_paddr - Destination start address. *
A 30 ; PRG_length - Source buffer length. *
A 31 ; PRG_bufaddr - Source buffer start address. *
A 32 ; *
A 33 ; The algorithm used is "row-horizontal" which means that *
A 34 ; an entire flash row (32 words) are programed in parallel. *
A 35 ; This method provides better uniformity of programming *
A 36 ; levels between adjacent bits then if each address were *
A 37 ; programed independently. The algorithm also uses a 3-read *
A 38 ; check for VER0 margin (i.e. The flash location is read *
A 39 ; three times and the first two values are discarded.) This *
A 40 ; provides low-freq read-back margin on programed bits. For *
A 41 ; example, if the flash is programmed using a CLKOUT period *
A 42 ; of 50ns, the flash can be reliably readback over the *
A 43 ; CLKOUT period range of 50ns to 150ns (6.67Mhz-20Mhz). *
A 44 ; The programming pulse-width is 100us, and a maximum of *
A 45 ; 150 pulses are applied per row. *
A 46 ; *
A 47 ; The following variables are used for temp storage: *
A 48 ; AR0 - Used for comparisons. *
A 49 ; AR1 - Used for pgm pulse count. *
A 50 ; AR2 - Used for row banz loop. *
A 51 ; AR3 - Used for buffer addr index. *
A 52 ; AR4 - Used for flash address. *
TMS320C1x/C2x/C2xx/C5x COFF Assembler Beta Version 6.63 Tue Nov 30 13:52:44 1999
Copyright (c) 1987-1996 Texas Instruments Incorporated
PRG24_X1.ABS PAGE 2
A 53 ; AR6 - Parameter passed to Delay. *
A 54 ; SPAD1 - Flash program and STOP commands. *
A 55 ; SPAD2 - Flash program + EXE command. *
A 56 ; FL_ADRS - Used for flash address. *
A 57 ; FL_DATA - Used for flash data. *
A 58 ; B2_0 - Used for row-done flag. *
A 59 ; B2_1 - Used for row start address. *
A 60 ; B2_2 - Used for row length-1. *
A 61 ; B2_3 - Used for buffer/row start addr. *
A 62 ; B2_4 - Used for destination end addr. **
A 63 ; DLY10 - Used for Delay repeat counter (DAF)
A 64 ; DLY100 - Used for Delay repeat counter (DAF)
A 65 ; DUMMY - Dummy variable
A 66 ;************************************************************
A 67
A 68 .include "svar2x.h"
A 69
A 70 0096 MAX_PGM .set 150 ;Only allow 150 pulses per row.
A 71 0010 VER0 .set 010h ;VER0 command.
A 72 0004 WR_CMND .set 4 ;Write command.
A 73 0045 WR_EXE .set 045h ;Write EXEBIN command.
A 74 0000 STOP .set 0 ;Reset command.
A 75
A 76 .def PROGRAM
A 77
A 78 ; .ref PRG_bufaddr,PRG_length,PRG_paddr
A 79 ; .ref PROTECT
A 80 ; .ref DELAY,REGS,ARRAY
A 81
A 82 fe66 .sect ".alg"
A 83
A 84 ;GPGMJ: SPLK #0,IMR ;MASK ALL INTERRUPTS - (DAF)
A 85 ; SETC INTM ;GLOBALLY MASK ALL INTERRUPTS
A 86 ; CALL PROGRAM ;Program flash.
A 87
A 88 ************************************************
A 89 * PROGRAM: This routine programs all or part of*
A 90 * the flash as specified by the variables: *
A 91 * PRG_paddr - Destination start address. *
A 92 * PRG_length - Source buffer length. *
A 93 * PRG_bufaddr - Buffer start address. *
A 94 * *
A 95 * The following variables are used for temp *
A 96 * storage: *
A 97 * AR0 - Used for comparisons. *
A 98 * AR1 - Used for pgm pulse count. *
A 99 * AR2 - Used for row banz loop. *
A 100 * AR3 - Used for buffer addr index. *
A 101 * FL_ADRS - Used for flash address. *
A 102 * FL_DATA - Used for flash data. *
A 103 * B2_0 - Used for row-done flag. *
A 104 * B2_1 - Used for row start address. *
A 105 * B2_2 - Used for row length-1. *
A 106 * B2_3 - Used for buffer/row start addr.*
TMS320C1x/C2x/C2xx/C5x COFF Assembler Beta Version 6.63 Tue Nov 30 13:52:44 1999
Copyright (c) 1987-1996 Texas Instruments Incorporated
PRG24_X1.ABS PAGE 3
A 107 * B2_4 - Used for destination end addr. *
A 108 ************************************************
A 109 fe66 PROGRAM
A 110 fe66 6909! LACL PRG_paddr ;Get destination start address.
A 111 fe67 901d! SACL FL_ADRS ;Save as current address.
A 112
A 113 fe68 200a! ADD PRG_length ;Determine destination end addr.
A 114 fe69 ba01 SUB #1 ;
A 115 fe6a 9011! SACL B2_4 ;Save destination end addr.
A 116 fe6b 6909! LACL PRG_paddr ;Get destination start addr.
A 117
A 118 fe6c 030b! LAR AR3,PRG_bufaddr ;Get buffer start address.
A 119 ********Begin a new row.*
A 120 fe6d NEWROW
A 121 fe6d 900e! SACL B2_1 ;Save row start address.
A 122 fe6e 8310! SAR AR3,B2_3 ;Save buffer/row start address.
A 123 fe6f b100 LAR AR1,#0 ;Init pulse count to zero.
A 124 fe70 ae0f! SPLK #31,B2_2 ;Init row length-1 to 31.
fe71 001f
A 125 fe72 bfb0 AND #001Fh ;Is start addr on row boundary?
fe73 001f
A 126 fe74 eb08 CC ADJ_ROW,NEQ ;If not then adjust row length.
fe75 feb6+
A 127 fe76 690e! LACL B2_1 ;Get row start address.
A 128 fe77 bfc0 OR #001Fh ;Get row end address.
fe78 001f
A 129 fe79 3011! SUB B2_4 ;Is end address on row boundary?
A 130 fe7a eb04 CC ADJ_ROW,GT ;If not then adjust row length.
fe7b feb6+
A 131 ********Same row, next pulse.*
A 132 fe7c SAMEROW
A 133 fe7c ae0d! SPLK #1,B2_0 ;Set row done flag = 1(True).
fe7d 0001
A 134 fe7e 690e! LACL B2_1 ;Get row start address.
A 135 fe7f 901d! SACL FL_ADRS ;Save as current address.
A 136 fe80 0310! LAR AR3,B2_3 ;Get buffer/row start addr.
A 137 fe81 020f! LAR AR2,B2_2 ;Init row index.
A 138 ********Repeat the following code 32 times or until end of row.*
A 139 ********First do low-byte.*
A 140
A 141 fe82 ae0c! LOBYTE SPLK #0FFh, BYTE_MASK ;Prepare mask for low byte
fe83 00ff
A 142 fe84 7a80 CALL PRG_BYTE
fe85 fea6+
A 143 fe86 ae0c! HIBYTE SPLK #0FF00h, BYTE_MASK ;Prepare mask for Hi byte
fe87 ff00
A 144 fe88 7a80 CALL PRG_BYTE
fe89 fea6+
A 145
A 146 ;LOBYTE
A 147 ; CALL SET_MODULE,AR4 ;Determine which flash module.
A 148 ; CALL SET_RD_VER0 ;Read word at VER0 level.
A 149 ; MAR *,AR3 ;ARP -> buffer addr index.
A 150 ; LACL * ;Get word to program.
TMS320C1x/C2x/C2xx/C5x COFF Assembler Beta Version 6.63 Tue Nov 30 13:52:44 1999
Copyright (c) 1987-1996 Texas Instruments Incorporated
PRG24_X1.ABS PAGE 4
A 151 ; XOR FL_DATA ;Xor with read-back value.
A 152 ; AND #0FFh ;Mask off hi-byte mask.
A 153 ; BCND HIBYTE,EQ ;If zero then done.
A 154 ; XOR #0FFFFh ;else, mask off good bits.
A 155 ; SACL FL_DATA ;New data.
A 156 ; CALL EXE_PGM ;PGM Pulse.
A 157 ; SPLK #0,B2_0 ;Set row done flag = 0(False).
A 158 ********Now do hi-byte.*
A 159 ;HIBYTE
A 160 ; CALL SET_RD_VER0 ;Read word at VER0 level.
A 161 ; MAR *,AR3 ;ARP -> buffer addr index.
A 162 ; LACL * ;Get word to program.
A 163 ; XOR FL_DATA ;Xor with read-back value.
A 164 ; AND #0FF00h ;Mask off lo-byte mask.
A 165 ; BCND NEXTWORD,EQ ;If zero then done.
A 166 ; XOR #0FFFFh ;else, mask off good bits.
A 167 ; SACL FL_DATA ;New data.
A 168 ; CALL EXE_PGM ;PGM Pulse.
A 169 ; SPLK #0,B2_0 ;Set row done flag = 0(False).
A 170 ********************
A 171
A 172 fe8a NEXTWORD
A 173 fe8a 691d! LACL FL_ADRS ;Load address for next word.
A 174 fe8b b801 ADD #1 ;Increment address.
A 175 fe8c 901d! SACL FL_ADRS ;Save as current address.
A 176 fe8d 8b8b MAR *, AR3 ;ARP -> buffer addr index.
A 177 fe8e 8baa MAR *+,AR2 ;Inc, and ARP -> row index.
A 178 fe8f 7b90 BANZ LOBYTE ;Do next word,and dec AR2.
fe90 fe82+
A 179 ********Reached end of row. Check if row done. *
A 180 fe91 4f0d! BIT B2_0,15 ;Get row_done flag.
A 181 fe92 e100 BCND ROW_DONE,TC ;If 1 then row is done.
fe93 fe9c+
A 182 fe94 8b89 MAR *,AR1 ;Else, row is not done, so
A 183 fe95 8ba0 MAR *+ ;inc row pulse count.
A 184 fe96 b096 LAR AR0,#MAX_PGM ;Check if passed allowable max.
A 185 fe97 bf46 CMPR 2 ;If AR1>MAX_PGM then
A 186 fe98 e100 BCND EXIT,TC ;fail, don't continue.
fe99 feef+
A 187 fe9a 7980 B SAMEROW ;else, go to beginning
fe9b fe7c+
A 188 ;of same row.
A 189 ********If row done then check if Array done. *
A 190 fe9c ROW_DONE
A 191 fe9c 691d! LACL FL_ADRS ;Check if end of array.
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