clr24_x1.lst

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C:\DSPTOOLS\FIX_663\DSPA.EXE -a CLR24_X1.ABS -v2xx 

TMS320C1x/C2x/C2xx/C5x COFF Assembler Beta Version 6.63  Tue Nov 30 13:52:43 1999
Copyright (c) 1987-1996  Texas Instruments Incorporated 
CLR24_X1.ABS                                                         PAGE    1

      47 3800                 .text
      48                      .copy       "CLR24_X1.ASM"
 A     1            *************************************************************
 A     2            ** CLEAR  Subroutine
 A     3            *
 A     4            * TMS320F2XX Flash Utilities.
 A     5            * Revision: 2.1   4 Dec 97
 A     6            *
 A     7            * Filename: CLR24_X1.ASM
 A     8            * Changes: Re-written to include latest flash algorithms.
 A     9            *
 A    10            *                DSP Applications
 A    11            *                Texas Instruments Inc.
 A    12            *
 A    13            * Change: Added Delay initialisation to the clear algorithm.
 A    14            *         This is also used by the Erase & Prog algs.
 A    15            *
 A    16            *
 A    17            * Called by : c2xx_bcx.asm or flash application programs.
 A    18            *
 A    19            * !!CAUTION - INITIALIZE DP BEFORE CALLING THIS ROUTINE!!
 A    20            *
 A    21            * Function  : Clears one or more contiguous segments of
 A    22            *             flash array 0/1 as specified by the fol
 A    23            *             -lowing variables.
 A    24            *             SEG_ST = Segment start address.
 A    25            *             SEG_END= Segment end address.
 A    26            *             PROTECT= Sector protect enable.
 A    27            *
 A    28            * The algorithm used is "row-horizontal" which means that
 A    29            * an entire flash row (32 words) are programed in parallel
 A    30            * This method provides better uniformity of programming
 A    31            * levels between adjacent bits then if each address were
 A    32            * programed independently. The algorithm also uses a 3-read
 A    33            * check for VER0 margin (i.e. The flash location is read
 A    34            * three times and the first two values are discarded.) This
 A    35            * provides low-freq read-back margin on programed bits. For
 A    36            * example, if the flash is programmed using a CLKOUT period
 A    37            * of 50ns, the flash can be reliably readback over the
 A    38            * CLKOUT period range of 50ns to 150ns (6.67Mhz-20Mhz).
 A    39            * The programming pulse-width is 100us, and a maximum of
 A    40            * 150 pulses are applied per row.
 A    41            *
 A    42            * The following resources are used for temporary storage:
 A    43            *        AR0  - Used for comparisons.
 A    44            *        AR1  - Used for pgm pulse count.
 A    45            *        AR2  - Used for row banz loop.
 A    46            *        AR6  - Parameter passed to Delay.
 A    47            *    FL_ADRS  - Used for flash address.
 A    48            *    FL_DATA  - Used for flash data.
 A    49            *      FL_ST  - Used for flash start address.
 A    50            *       B2_0  - Used for row-done flag.
 A    51            *       B2_1  - Used for row start address.
 A    52            *      SPAD1  - Flash commands.
TMS320C1x/C2x/C2xx/C5x COFF Assembler Beta Version 6.63  Tue Nov 30 13:52:43 1999
Copyright (c) 1987-1996  Texas Instruments Incorporated 
CLR24_X1.ABS                                                         PAGE    2

 A    53            *      SPAD2  - Flash commands.
 A    54            *
 A    55            *************************************************************
 A    56                    .include "svar2X.h"
 A    57            *
 A    58      0096  MAX_PGM .set    150        ;Only allow 150 pulses per row.
 A    59      0010  VER0    .set    010h       ;VER0 command.
 A    60      0004  WR_CMND .set    4          ;Write command.
 A    61      0045  WR_EXE  .set    045h       ;Write EXEBIN command.
 A    62      0000  STOP    .set    0          ;Reset command.
 A    63            
 A    64                    .def    CLEAR
 A    65            
 A    66            ;       .def    GCLR
 A    67            ;       .ref    PROTECT,SEG_ST,SEG_END
 A    68            ;       .ref    DELAY,REGS,ARRAY
 A    69            
 A    70            ;       .sect   "clr_flsh"
 A    71 fe66               .sect   ".alg"
 A    72            
 A    73            ;GCLR:   SPLK    #0,IMR          ;MASK ALL INTERRUPTS
 A    74            ;       SETC    INTM            ;GLOBALLY MASK ALL INTERRUPTS
 A    75            ;       CLRC    SXM             ;Disable sign extension.
 A    76            
 A    77            
 A    78            ;       CALL    CLEAR           ;Clear the specified segments.
 A    79            
 A    80            ************************************************
 A    81            * CLEAR:    This routine performs a clear opera*
 A    82            * -tion on the flash array defined by the FL_ST*
 A    83            * variable. The segments to be cleared are     *
 A    84            * defined by the SEG_ST, SEG_END, and PROTECT  *
 A    85            * variables.                                   *
 A    86            * The following resources are used for temp    *
 A    87            * storage:                                     *
 A    88            *        AR0  - Used for comparisons.          *
 A    89            *        AR1  - Used for pgm pulse count.      *
 A    90            *        AR2  - Used for row banz loop.        *
 A    91            *    FL_ADRS  - Used for flash address.        *
 A    92            *    FL_DATA  - Used for flash data.           *
 A    93            *        B2_0 - Used for row-done flag.        *
 A    94            *        B2_1 - Used for row start address.    *
 A    95            ************************************************
 A    96 fe66       CLEAR:
 A    97 fe66 691a!         LACL    SEG_ST                  ;Get segment start address.
 A    98 fe67 901d!         SACL    FL_ADRS                 ;Save as current address.
 A    99            ;       LACL    SEG_ST                  ;Get segment start address.
 A   100 fe68 bfb0          AND     #04000h                 ;Get array start address.
         fe69 4000  
 A   101 fe6a 9021!         SACL    FL_ST                   ;Save array start address.
 A   102            
 A   103            ;Initialisation of Delay values are done only here in the Clear alg.
 A   104            ;Erase & Program algs rely on these values also. (DAF)
 A   105 fe6b ae17!         SPLK    #0200, DLY10            ;Delay val for 10uS
TMS320C1x/C2x/C2xx/C5x COFF Assembler Beta Version 6.63  Tue Nov 30 13:52:43 1999
Copyright (c) 1987-1996  Texas Instruments Incorporated 
CLR24_X1.ABS                                                         PAGE    3

         fe6c 00c8  
 A   106 fe6d ae18!         SPLK    #2000, DLY100           ;Delay val for 100uS
         fe6e 07d0  
 A   107 fe6f ae19!         SPLK    #0FFFFh, DLY3K3         ;Dealy val for 3.3mS
         fe70 ffff  
 A   108            
 A   109            ********Begin a new row.*
 A   110 fe71       NEWROW
 A   111 fe71 900e!         SACL    B2_1                    ;Save row start address.
 A   112 fe72 b100          LAR     AR1,#0                  ;Init pulse count to zero.
 A   113            ********Same row, next pulse.*
 A   114 fe73       SAMEROW
 A   115 fe73 ae0d!         SPLK    #1,B2_0                 ;Set row done flag = 1(True).
         fe74 0001  
 A   116 fe75 690e!         LACL    B2_1                    ;Get row start address.
 A   117 fe76 901d!         SACL    FL_ADRS                 ;Save as current address.
 A   118 fe77 b21f          LAR     AR2,#31                 ;Init row index.
 A   119            ********Repeat the following code 32 times until end of row.*
 A   120            ********First do low-byte.*
 A   121 fe78       LOBYTE                                  
 A   122 fe78 7a80          CALL    SET_RD_VER0             ;Read word at VER0 level.
         fe79 fecc+ 
 A   123 fe7a b9ff          LACL    #0FFh                   ;Get lo-byte mask.
 A   124 fe7b 6e1e!         AND     FL_DATA                 ;Xor with read-back value.
 A   125 fe7c e388          BCND    HIBYTE,EQ               ;If zero then done.
         fe7d fe85+ 
 A   126 fe7e bfd0          XOR     #0FFFFh                 ;else, mask off good bits.
         fe7f ffff  
 A   127 fe80 901e!         SACL    FL_DATA                 ;New data.
 A   128 fe81 7a80          CALL    EXE_PGM                 ;PGM Pulse.
         fe82 feb1+ 
 A   129 fe83 ae0d!         SPLK    #0,B2_0                 ;Set row done flag = 0(False).
         fe84 0000  
 A   130            ********Now do hi-byte.*
 A   131 fe85       HIBYTE
 A   132 fe85 7a80          CALL    SET_RD_VER0             ;Read word at VER0 level.
         fe86 fecc+ 
 A   133 fe87 bf80          LACC    #0FF00h                 ;Get hi-byte mask.
         fe88 ff00  
 A   134 fe89 6e1e!         AND     FL_DATA                 ;And with read-back value.
 A   135 fe8a e388          BCND    NEXTWORD,EQ             ;If zero then done.
         fe8b fe93+ 
 A   136 fe8c bfd0          XOR     #0FFFFh                 ;else, mask off good bits.
         fe8d ffff  
 A   137 fe8e 901e!         SACL    FL_DATA                 ;New data.
 A   138 fe8f 7a80          CALL    EXE_PGM                 ;PGM Pulse.
         fe90 feb1+ 
 A   139 fe91 ae0d!         SPLK    #0,B2_0                 ;Set row done flag = 0(False).
         fe92 0000  
 A   140            ********************
 A   141 fe93       NEXTWORD
 A   142 fe93 691d!         LACL    FL_ADRS                 ;Load address for next word.
 A   143 fe94 b801          ADD     #1                      ;Increment address.
 A   144 fe95 901d!         SACL    FL_ADRS                 ;Save as current address.
TMS320C1x/C2x/C2xx/C5x COFF Assembler Beta Version 6.63  Tue Nov 30 13:52:43 1999
Copyright (c) 1987-1996  Texas Instruments Incorporated 
CLR24_X1.ABS                                                         PAGE    4