divider.vhd

一个用VHDL语言编写的除法器程序

Library IEEE ;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
ENTITY divider IS
PORT(clk 		: IN STD_LOGIC;                           --计数时钟
	 divisor 	: IN STD_LOGIC_VECTOR(27 DOWNTO 0);       --除数
	quotient   	: OUT STD_LOGIC_VECTOR(27 DOWNTO 0));	  --除法器结果
END divider;
ARCHITECTURE rtl OF divider IS
	--7位BCD减法器
	COMPONENT subtracter_bcd7
		PORT(
		   a 		: IN STD_LOGIC_VECTOR(27 DOWNTO 0);       --被减数
		   b 		: IN STD_LOGIC_VECTOR(27 DOWNTO 0);       --减数
		   cin      : IN STD_LOGIC;							  --借位输入
		   c   		: OUT STD_LOGIC_VECTOR(27 DOWNTO 0);      --差
		   cout		: OUT STD_LOGIC);	                      --借位输出
	END COMPONENT;
	--7位BCD加法计数器
	COMPONENT counter_bcd7
		PORT(clr,ena,clk          	 : IN STD_LOGIC;   --clr计数器清零，en计数使能，clk时钟
			 q      				 : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);--计数器输出，该语句用于实际应用
			 zeros	 			     : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
			 cout					 : OUT STD_LOGIC); --计数器进位
	END COMPONENT;
	--7位BCD减法计数器
	COMPONENT counter_bcd7_down
		PORT(clr,ena,clk          	 : IN STD_LOGIC;   --clr计数器清零，en计数使能，clk时钟
	         preset					 : IN STD_LOGIC;   --预置数
			 q      				 : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);--计数器输出
			 zero	 			     : OUT STD_LOGIC ); --计数器的值为0
	END COMPONENT;
	--高、低电平
	SIGNAL low,high  				: STD_LOGIC;
	--减法器的输入输出信号
	SIGNAL sub_b    				: STD_LOGIC_VECTOR(27 DOWNTO 0);
	SIGNAL sub_c    				: STD_LOGIC_VECTOR(27 DOWNTO 0);
	SIGNAL sub_c_reg   				: STD_LOGIC_VECTOR(27 DOWNTO 0);
	SIGNAL sub_cout  				: STD_LOGIC;
	SIGNAL sub_cout_reg   			: STD_LOGIC;
	--7位BCD加法计数器输入输出信号
	SIGNAL count_up_ena   			: STD_LOGIC;
	SIGNAL count_up_clr   			: STD_LOGIC;
	SIGNAL count_up_q   			: STD_LOGIC_VECTOR(27 DOWNTO 0);	
	SIGNAL count_up_zeros           : STD_LOGIC_VECTOR(6 DOWNTO 0);
	SIGNAL count_up_cout            : STD_LOGIC;
	--7位BCD减法计数器输入输出信号
	SIGNAL count_down_ena   		: STD_LOGIC;
	SIGNAL count_down_preset  		: STD_LOGIC;
	SIGNAL count_down_zero			: STD_LOGIC;
	SIGNAL count_down_q 			: STD_LOGIC_VECTOR(27 DOWNTO 0);
	--寄存器A,B,C控制信号
	SIGNAL reg_a_load				: STD_LOGIC;
	SIGNAL reg_b_clr				: STD_LOGIC;
	SIGNAL reg_c_load				: STD_LOGIC;
	--状态机状态(ONE-HOT状态机)
	CONSTANT s0                     : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001";
	CONSTANT s1                     : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010";
	CONSTANT s2                     : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100";
	SIGNAL present_state			: STD_LOGIC_VECTOR(2 DOWNTO 0);
	SIGNAL next_state				: STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
	low <= '0';
	high <= '1';
	--7位BCD加法计数器
	count_up:counter_bcd7
	PORT MAP
		(	clr => count_up_clr,
			ena => count_up_ena,
			clk => clk,
			q => count_up_q,
			zeros => count_up_zeros,
			cout => count_up_cout);
	--7位BCD减法计数器
	count_down:counter_bcd7_down
	PORT MAP
		(	clr => low,
			ena => sub_cout_reg,
			clk => clk,
			preset => count_down_preset,
			q => count_down_q,
			zero => count_down_zero);
	--减法器
	sub:subtracter_bcd7
	PORT MAP
		(	a => sub_c_reg,
			b => sub_b,
			cin => low,
			c => sub_c,
			cout => sub_cout); 
	--寄存器A,B,C
	PROCESS(clk)
	BEGIN
		IF(clk'event AND clk='1')THEN
			IF(reg_a_load = '1')THEN
				sub_b <= divisor;
			END IF;
			IF(reg_b_clr = '1')THEN
				sub_c_reg <= (OTHERS => '0');
				sub_cout_reg <= '0';
			ELSE
			    sub_c_reg <= sub_c;
				sub_cout_reg <= sub_cout;
			END IF;
			IF(reg_c_load = '1')THEN
				quotient <= count_up_q;
			END IF;
		END IF;
	END PROCESS;
	--状态机的状态更新
	PROCESS(clk)
	BEGIN
		IF(clk'event AND clk='1')THEN
			present_state <= next_state;
		END IF;		
	END PROCESS;
	--状态机的状态译码
	PROCESS(present_state,count_down_zero)
	BEGIN
		CASE present_state IS
			WHEN s0 => next_state <= s1;
			WHEN s1 => 
					IF(count_down_zero ='1')THEN
						next_state <= s2;
					ELSE
						next_state <= s1;
					END IF;
			WHEN s2 =>
					next_state <= s0;
			WHEN OTHERS =>
					next_state <= s0;
		END CASE;
	END PROCESS;
	--状态机的输出译码
	PROCESS(present_state)
	BEGIN
		CASE present_state IS
			WHEN s0 =>
				reg_a_load <= '1';
				reg_b_clr <='1';
				reg_c_load <= '0';
				count_up_clr <= '1';
				count_up_ena <= '0';		
				count_down_preset <= '1';				
			WHEN s1 =>
				reg_a_load <= '0';
				reg_b_clr <='0';
				reg_c_load <= '0';
				count_up_clr <= '0';
				count_up_ena <= '1';		
				count_down_preset <= '0';	
			WHEN s2 =>
				reg_a_load <= '0';
				reg_b_clr <='0';
				reg_c_load <= '1';
				count_up_clr <= '0';
				count_up_ena <= '1';		
				count_down_preset <= '0';
			WHEN OTHERS =>
				reg_a_load <= '1';
				reg_b_clr <='1';
				reg_c_load <= '0';
				count_up_clr <= '1';
				count_up_ena <= '0';		
				count_down_preset <= '1';				
		END CASE;
	END PROCESS;
END RTL;