mx1_scm.h

mc9328mx1在UCOS操作系统下的SCM原代码

/*
 * mx1_scm.h
 * Define the register sets of System Control and Reset Module
 * Date	: 2004/02/25
 * By	: Zhang Jing
 */

#ifndef	MX1_SCM_H
#define	MX1_SCM_H

#include	"mx1.h"

#ifdef	MX1_SCM_FLAG
	#define	MX1_SCM_EXT
#else
	#define	MX1_SCM_EXT	extern
#endif


/* Define the register set structure */
typedef	struct struct_mx1_scm{
	mx1_reg		RSR;
	mx1_reg		SIDR;
	mx1_reg		FMCR;
	mx1_reg		GPCR;
	mx1_reg		GCCR;
} T_MX1_SCM;

/* Base address pointer of System Control and Reset Module */
#define	MX1_SCM	((T_MX1_SCM*)0x0021b800)

/* Useful macros */
// Hardware Reset Source determination
#define	RST_BY_POR()		(!((MX1_SCM->RSR)&0x3))			// Reset by Power on Reset
#define	RST_BY_EXT()		(((MX1_SCM->RSR)&0x3)==0x1)		// Reset by qualified external reset
#define	RST_BY_WAT()		(((MX1_SCM->RSR)&0x3)==0x2)		// Reset by Watchdog time out
// Get the silicon ID
#define	SILICON_ID()		(MX1_SCM->SIDR)
// Function Multiplexing Control Register
#define	SPI2_RXD_SEL_PA1		(0x0<<8)
#define	SPI2_RXD_SEL_PD9		(0x1<<8)
#define	SSI_RXFS_SEL_PC3		(0x0<<7)
#define	SSI_RXFS_SEL_PB14		(0x1<<7)
#define	SSI_RXCLK_SEL_PC4		(0x0<<6)
#define	SSI_RXCLK_SEL_PB15		(0x1<<6)
#define	SSI_RXDAT_SEL_PC5		(0x0<<5)
#define	SSI_RXDAT_SEL_PB16		(0x1<<5)
#define	SSI_TXFS_SEL_PC7		(0x0<<4)
#define	SSI_TXFS_SEL_PB18		(0x1<<4)
#define	SSI_TXCLK_SEL_PC8		(0x0<<3)
#define	SSI_TXCLK_SEL_PB19		(0x1<<3)
#define	EXT_BR_EN_MASK		(0x0<<2)
#define	EXT_BR_EN_ENABLE		(0x1<<2)
#define	SDCS1_SEL_CS3			(0x0<<1)
#define	SDCS1_SEL_CSD1		(0x1<<1)
#define	SDCS0_SEL_CS2			(0x0<<0)
#define	SDCS0_SEL_CSD0		(0x1<<0)
// Global Peripheral Control Register
#define	TEST_EN_REG_NORMAL		(0x0<<15)
#define	TEST_EN_REG_DEBUG		(0x1<<15)
#define	BTAEN_DISABLE			(0x0<<12)
#define	BTAEN_ENABLE			(0x1<<12)
#define	DS_SLOW_26M15F		(0x0<<10)
#define	DS_SLOW_26M30F		(0x1<<10)
#define	DS_SLOW_26M45F		(0x2<<10)
#define	DS_SLOW_26MGT45F		(0x3<<10)
#define	DS_CNTL_50M15F		(0x0<<8)
#define	DS_CNTL_50M30F		(0x1<<8)
#define	DS_CNTL_100M15F		(0x2<<8)
#define	DS_CNTL_100M30F		(0x3<<8)
#define	DS_ADDR_50M15F		(0x0<<6)
#define	DS_ADDR_50M30F		(0x1<<6)
#define	DS_ADDR_100M15F		(0x2<<6)
#define	DS_ADDR_100M30F		(0x3<<6)
#define	DS_DATA_50M15F		(0x0<<4)
#define	DS_DATA_50M30F		(0x1<<4)
#define	DS_DATA_100M15F		(0x2<<4)
#define	DS_DATA_100M30F		(0x3<<4)
#define	MMA_PROT_EN_ALL		(0x0<<1)
#define	MMA_PROT_EN_PRIVIL		(0x1<<1)
#define	CSI_PROT_EN_ALL		(0x0<<0)
#define	CSI_PROT_EN_PRIVIL		(0x1<<0)
// Global Clock Control
#define	UART3_CLK_DISABLE		(0x0<<6)
#define	UART3_CLK_ENABLE		(0x1<<6)
#define	SSI2_CLK_DISABLE		(0x0<<5)
#define	SSI2_CLK_ENABLE		(0x1<<5)
#define	BROM_CLK_BOOT			(0x0<<4)
#define	BROM_CLK_HCLK			(0x1<<4)
#define	DMA_CLK_DISABLE		(0x0<<3)
#define	DMA_CLK_ENABLE		(0x1<<3)
#define	CSI_CLK_DISABLE		(0x0<<2)
#define	CSI_CLK_ENABLE			(0x1<<2)
#define	MMA_CLK_DISABLE		(0x0<<1)
#define	MMA_CLK_ENABLE		(0x1<<1)
#define	USBD_CLK_DISABLE		(0x0<<0)
#define	USBD_CLK_ENABLE		(0x1<<0)

#endif