mx1_ssi.h

mc9328mx1在UCOS操作系统下的SSI原代码

/*
 * mx1_ssi.h
 * Define the register set for Synchronous Serial Interface
 * By	: Jing Zhang
 * Date	: 2004/06/09
 */

#ifndef	MX1_SSI_H
#define	MX1_SSI_H

#include	"mx1.h"

#ifdef	MX1_SSI_FLAG
	#define	MX1_SSI_EXT
#else
	#define	MX1_SSI_EXT	extern
#endif

// Define the register set structure
typedef struct struct_mx1_ssi{
	mx1_reg		STX;
	mx1_reg		SRX;
	mx1_reg		SCSR;
	mx1_reg		STCR;
	mx1_reg		SRCR;
	mx1_reg		STCCR;
	mx1_reg		SRCCR;
	mx1_reg		STSR;
	mx1_reg		SFCSR;
	mx1_reg		Reserved;
	mx1_reg		SOR;
} T_MX1_SSI;

// Base address pointer of SSI
#define	MX1_SSI1		((T_MX1_SSI*)0x00218000)
#define	MX1_SSI2		((T_MX1_SSI*)0x0021d000)

// Useful macros
// SSI Control/Status Register
#define	SCSR_SYS_CLK_ENABLE		(1<<15)
#define	SCSR_SYS_CLK_DISABLE		(0<<15)

#define	SCSR_I2S_MODE_NORMAL		(0<<13)
#define	SCSR_I2S_MODE_MASTER		(1<<13)
#define	SCSR_I2S_MODE_SLAVE		(2<<13)

#define	SCSR_SYN_ENABLE		(1<<12)
#define	SCSR_SYN_DISABLE		(0<<12)

#define	SCSR_NET_NETWORK		(1<<11)
#define	SCSR_NET_NORMAL		(0<<11)

#define	SCSR_RE_ENABLE		(1<<10)
#define	SCSR_RE_DISABLE		(0<<10)

#define	SCSR_TE_ENABLE		(1<<9)
#define	SCSR_TE_DISABLE		(0<<9)

#define	SCSR_SSI_ENABLE		(1<<8)
#define	SCSR_SSI_DISABLE		(0<<8)

#define	SCSR_RDR			(1<<7)

#define	SCSR_TDE			(1<<6)

#define	SCSR_ROE			(1<<5)

#define	SCSR_TUE			(1<<4)

#define	SCSR_TFS			(1<<3)

#define	SCSR_RFS			(1<<2)

#define	SCSR_RFF			(1<<1)

#define	SCSR_TFE			(1<<0)
// SSI Transmit Configuration Register
#define	STCR_TXBIT0_15			(0<<10)
#define	STCR_TXBIT0_0			(1<<10)

#define	STCR_TDMAE_ENABLE		(1<<9)
#define	STCR_TDMAE_DISABLE		(0<<9)

#define	STCR_TIE_DISABLE		(0<<8)
#define	STCR_TIE_ENABLE		(1<<8)

#define	STCR_TFEN_DISABLE		(0<<7)
#define	STCR_TFEN_ENABLE		(1<<7)

#define	STCR_TFDIR_EXT			(0<<6)
#define	STCR_TFDIR_INT			(1<<6)

#define	STCR_TXDIR_EXT			(0<<5)
#define	STCR_TXDIR_INT			(1<<5)

#define	STCR_TSHFD_MSB		(0<<4)
#define	STCR_TSHFD_LSB		(1<<4)

#define	STCR_TSCKP_RISING		(0<<3)
#define	STCR_TSCKP_FALLING		(1<<3)

#define	STCR_TFSI_HIGH			(0<<2)
#define	STCR_TFSI_LOW			(1<<2)

#define	STCR_TFSL_WORD		(0<<1)
#define	STCR_TFSL_BIT			(1<<1)

#define	STCR_TEFS_FIRST_DATA		(0<<0)
#define	STCR_TEFS_BIT_CLOCK		(1<<0)
//SSI Receive Configuration Register
#define	SRCR_RXBIT0_15			(0<<10)
#define	SRCR_RXBIT0_0			(1<<10)

#define	SRCR_RDMAE_ENABLE		(0<<9)
#define	SRCR_RDMAE_DISABLE		(1<<9)

#define	SRCR_RIE_DISABLE		(0<<8)
#define	SRCR_RIE_ENABLE		(1<<8)

#define	SRCR_RFEN_DISABLE		(0<<7)
#define	SRCR_RFEN_ENABLE		(1<<7)

#define	SRCR_RFDIR_EXT			(0<<6)
#define	SRCR_RFDIR_INT			(1<<6)

#define	SRCR_RXDIR_EXT			(0<<5)
#define	SRCR_RXDIR_INT			(1<<5)

#define	SRCR_RSHFD_MSB		(0<<4)
#define	SRCR_RSHFD_LSB		(1<<4)

#define	SRCR_RSCKP_FALLING		(0<<3)
#define	SRCR_RSCKP_RISING		(1<<3)

#define	SRCR_RFSI_HIGH			(0<<2)
#define	SRCR_RFSI_LOW			(1<<2)

#define	SRCR_RFSL_WORD		(0<<1)
#define	SRCR_RFSL_BIT			(1<<1)

#define	SRCR_REFS_FIRST_DATA		(0<<0)
#define	SRCR_REFS_BIT_CLOCK		(1<<0)

// SSI Transmit Clock Control Register
#define	STCCR_PSR_BYPASS		(0<<15)
#define	STCCR_PSR_USE			(1<<15)

#define	STCCR_WL_8			(0<<13)
#define	STCCR_WL_10			(1<<13)
#define	STCCR_WL_12			(2<<13)
#define	STCCR_WL_16			(3<<13)

#define	STCCR_DC( ratio )		(((ratio)&0x1f)<<8)

#define	STCCR_PM( ratio )		(((ratio)&&0xff)<<0)

// SSI Receive Clock Control Register
#define	SRCCR_PSR_BYPASS		(0<<15)
#define	SRCCR_PSR_USE			(1<<15)

#define	SRCCR_WL_8			(0<<13)
#define	SRCCR_WL_10			(1<<13)
#define	SRCCR_WL_12			(2<<13)
#define	SRCCR_WL_16			(3<<13)

#define	SRCCR_DC( ratio )		(((ratio)&0x1f)<<8)

#define	SRCCR_PM( ratio )		(((ratio)&&0xff)<<0)

// Time Slot Register
#define	STSR_DUMMY( dum )		((dum)&0xffff)


// FIFO ControlStatus Register
#define	SFCSR_RFCNT( ssi )		(((ssi)->SFCSR)>>12)

#define	SFCSR_TFCNT( ssi )		((((ssi)->SFCSR)>>8)&0xf)

#define	SFCSR_RFWM( val )		(((val)&0xf)<<4)

#define	SFCSR_TFWM( val )		(((val)&0xf)<<0)

// Option Register
#define	SOR_CLKOFF_ENABLE		(0<<6)
#define	SOR_CLKOFF_DISABLE		(1<<6)

#define	SOR_RX_CLR			(1<<5)
#define	SOR_TX_CLR			(1<<4)
#define	SOR_SYNRST			(1<<0)

//////////////////////////////////////////////
// SSI use GPIO for muxing
#define	SSI_GPIO_PORT			MX1_GPIO_PC

// CS4340 Related
#define	CS4340_RESET()			DR_HIGH(MX1_GPIO_PB, 17)
/* Function prototypes */
MX1_SSI_EXT void MX1_SSI_Init(T_MX1_SSI * ssi_module);
MX1_SSI_EXT void MX1_SSI_Write(T_MX1_SSI * ssi_module, unsigned int val);

#endif