memsetup.s

mc9328mx1的mem分配原代码

SDRAMC_BASE_ADDR	EQU	0x00221000
CSD0_BASE_ADDR		EQU	0x08000000
;#define PRE_ALL_CMD         0x91120300    ;0x92120200,IAM=0    ;0x921A0200,IAM=1
PRE_ALL_CMD		EQU	0x92120200
ISSUE_PRE		EQU	0x08200000
;#define AUTO_REF_CMD        0xA1120300
AUTO_REF_CMD		EQU	0xA2120200
SET_MODE_REG_CMD	EQU	0xB2120200
MODE_REG_VAL0		EQU	0x08111800
NORMAL_MODE		EQU	0x82124200
;#define SET_MODE_REG_CMD    0xB1120300     ;;0xB2120200            ;0xB21A0200
;#define MODE_REG_VAL0       0x08119800      ;;0x08111800;      ;0x08446000
;#define NORMAL_MODE         0x81124300     ;;0x82124200            ;0x821AC300

CS1_CTRLH		EQU	0x00220008
CS1_CTRLL		EQU	0x0022000C

CCM_BASE		EQU	0x0021B000 
CCM_CSCR        	EQU	(CCM_BASE+0x00)
CCM_MPCTL0		EQU	(CCM_BASE+0x04)
CCM_PCDR		EQU	(CCM_BASE+0x20)

AITC_BASE		EQU	0x00223000
;#define AITC_NIMASK         (AITC_BASE+0x04)
;#define AITC_INTENNUM       (AITC_BASE+0x08)
AITC_INTTYPEH		EQU	(AITC_BASE+0x18)
AITC_INTTYPEL		EQU	(AITC_BASE+0x1C)
;#define AITC_NIPRIORITY1    (AITC_BASE+0x38)
;#define AITC_NIVECSR        (AITC_BASE+0x40)


	AREA	INIT_CRITICAL, CODE, READONLY

	EXPORT memsetup
memsetup
	;check whether the SDRAM has been configured
	ldr	r1, =SDRAMC_BASE_ADDR
	ldr	r0, [r1]
	ldr	r2, =0x80000000
	tst	r0, r2
	bne	out
      ; 1: Put SDRAM in precharge command mode*/
      ldr   r0  , =PRE_ALL_CMD
      ldr   r1  , =SDRAMC_BASE_ADDR
      str   r0  , [r1]

      ; Issue Precharge Command */
      ldr   r0  , =ISSUE_PRE
      ldr   r1  , [r0]

      ; 2: Set AutoRefresh Command */
      ldr   r0  , =AUTO_REF_CMD
      ldr   r1  , =SDRAMC_BASE_ADDR
      str   r0  , [r1]

      ; Issue Autorefresh Command */
      ldr   r1  , =CSD0_BASE_ADDR
      mov   r2  , #0x00
loop
      ldr   r0 , [r1]
      add   r2 ,  r2, #0x1
      cmp   r2 , #8
      bls   loop

      ; Set Mode register */
      ldr   r0  , =SET_MODE_REG_CMD
      ldr   r1  , =SDRAMC_BASE_ADDR
      str   r0  , [r1]
      
      ; Special read */ 
      ldr   r0  , =MODE_REG_VAL0
      ldr   r1  , [r0]

      ; Set to Normal mode */
      ldr   r0  , =NORMAL_MODE
      ldr   r1  , =SDRAMC_BASE_ADDR
      str   r0  , [r1]
	
      ; need static flash init */
 
      ; SRAM initialization */
      ldr   r0  , = 0x00000A00 
      ldr   r1  , = CS1_CTRLH
      str   r0  , [r1]

      ldr   r0  , = 0x11110601
      ldr   r1  , = CS1_CTRLL
      str   r0  , [r1]
      

      ; setting for 150 MHz MCU PLL CLK */
      ldr   r0  , = 0x04632410
      ;ldr   r0  , = 0x003f1437            ;CHENG LEI :setting for 196 MHz MCU PLL CLK*/
      ldr   r1  , = CCM_MPCTL0
      str   r0  , [r1]
      
      ; set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and  */
      ldr   r1 , = 0xAF000403
;      ldr   r1 , = 0xAF000003             ;CHENG LEI*/
      ldr   r0 , = CCM_CSCR
      str   r1 , [r0]

      ldr   r1 , = 0x000b000b             ;CHENG LEI*/
      ldr   r0 , = CCM_PCDR
      str   r1 , [r0]

      ; Trigger the restart bit(bit 21) */
      ldr   r2 , = 0x00200000
      orr   r2 , r2, r1
      str   r2 , [r0]
 
      ; Program PRESC bit(bit 15) to 0 to divide-by-1 */
      mov   r1 , r2 
      ldr   r2 , = 0xFFFF7FFF
      and   r2 , r2, r1      
      str   r2 , [r0]

	  ; async */
      mrc p15,0,r0,c1,c0,0
      ldr r2, =0xC0000000
      orr r0,r2,r0
      mcr p15,0,r0,c1,c0,0
					 
      ; all sources selected as normal interrupt */
      mov  r0 , #0x0
 
      ldr  r1  , = AITC_INTTYPEH 
      str  r0  , [r1]
      ldr  r1  , = AITC_INTTYPEL
      str  r0  , [r1]
      

      ; Initialize the flash */
      ldr   r1 , = 0x00001000
      ldr   r0 , = 0x00220000
      str   r1 , [r0]
 
	  ; end add additional*/
out
      mov   pc  , lr
      
      END