init.s

mc9328mx1的初始化原代码,ini.h

	INCLUDE	arm.inc
	INCLUDE	MemMap.inc
	INCLUDE mx1_dev.inc


	AREA	Start, CODE, READONLY
	
	ENTRY
	EXPORT	boot
boot

;- This table will be copied to external SRAM laterly.
VectorTable
	LDR	PC, Rst_vec
	LDR	PC, Und_vec
	LDR	PC, SWI_vec
	LDR	PC, Pre_vec
	LDR	PC, Dat_vec
	NOP
	LDR	PC, IRQ_vec
	LDR	PC, FIQ_vec


Rst_vec		DCD	Reset
Und_vec		DCD	UndefHandler
SWI_vec		DCD	SWIHandler
Pre_vec		DCD	PrefetchAbortHandler
Dat_vec		DCD	DataAbortHandler
IRQ_vec		DCD	IRQHandler
FIQ_vec		DCD	FIQHandler

;- Vectoring Execution function run at absolut addresss

SoftReset
		B	Reset
UndefHandler    
		LDR	R0, =DR_C
		LDR	R1, =0x04000000
		STR	R1, [R0]
              	B	UndefHandler
SWIHandler
                B	SWIHandler
PrefetchAbortHandler
		LDR	R0, =DR_C
		LDR	R1, =0x01000000
		STR	R1, [R0]
                B	PrefetchAbortHandler
DataAbortHandler
		LDR	R0, =DR_C
		LDR	R1, =0x02000000
		STR	R1, [R0]
                B	DataAbortHandler
IRQHandler	
		B	IRQ_com
FIQHandler	
		B	FIQHandler

Reset
		
		
; Initialize the memory system and clock

	IMPORT	memsetup
	BL	memsetup
	
;- Copy the VectorTable to the beginning of the external SRAM
		LDR	R8, =VectorTable
		LDR	R9, =xSRAM_BASE
		LDMIA	R8!, {R0-R7}
		STMIA	R9!, {R0-R7}
		LDMIA	R8!, {R0-R6}
		STMIA	R9!, {R0-R6}
		

;- Set up the stack pointer for each mode

;- Set the stack in embedded SRAM
;- Do not go to user mode, because the peripheral register can only be accessed in privileged mode
;- the uc/OS-ii will run in system mode all the time
	LDR	R0, =eSRAM_LIMIT
	
	;- Set the IRQ mode stack
	MSR	CPSR_c, #ARM_MODE_IRQ:OR:I_BIT:OR:F_BIT
	MOV	SP, R0
	SUB	R0, R0, #IRQ_STACK_SIZE

	;- Set the FIQ mode stack
	MSR	CPSR_c, #ARM_MODE_FIQ:OR:I_BIT:OR:F_BIT
	MOV	SP, R0
	SUB	R0, R0, #FIQ_STACK_SIZE
		
	;- Set the UND mode stack
	MSR	CPSR_c, #ARM_MODE_UND:OR:I_BIT:OR:F_BIT
	MOV	SP, R0
	SUB	R0, R0, #UND_STACK_SIZE
	
	;- Set the ABT mode stack
	MSR	CPSR_c, #ARM_MODE_ABT:OR:I_BIT:OR:F_BIT
	MOV	SP, R0
	SUB	R0, R0, #ABT_STACK_SIZE
	
	;- Set the SVC mode stack
	MSR	CPSR_c, #ARM_MODE_SVC:OR:I_BIT:OR:F_BIT
	MOV	SP, R0
	SUB	R0, R0, #SVC_STACK_SIZE
		
	;- Set the SYS mode stack and enable interrupts
	MSR	CPSR_c, #ARM_MODE_SYS
	MOV	SP, R0


;- Initialize the C variables

	IMPORT      |Image$$RO$$Limit|      ; End of ROM code (=start of ROM data)
	IMPORT      |Image$$RW$$Base|       ; Base of RAM to initialise
	IMPORT      |Image$$ZI$$Base|       ; Base and limit of area
	IMPORT      |Image$$ZI$$Limit|      ; to zero initialise

	LDR         R0, =|Image$$RO$$Limit| ; Get pointer to ROM data
	LDR         R1, =|Image$$RW$$Base|  ; and RAM copy
	LDR         R3, =|Image$$ZI$$Base|  ; Zero init base => top of initialised data
	CMP         R0, R1                  ; Check that they are different
	BEQ         NoRW
LoopRw	CMP         R1, R3                  ; Copy init data
	LDRCC       R2, [R0], #4
	STRCC       R2, [R1], #4
	BCC         LoopRw
NoRW	LDR         R1, =|Image$$ZI$$Limit| ; Top of zero init segment
	MOV         R2, #0
LoopZI	CMP         R3, R1                  ; Zero init
	STRCC       R2, [R3], #4
	BCC         LoopZI


	IMPORT  __main
	B	__main
	

;- IRQ common process procedure
	IMPORT	IRQ_Table

IRQ_com
	SUB	SP, SP, #4
	STMFD	SP!, {R0, R1}
	
		
	LDR	R0, =AITC_NIVECSR		; Get the interrupt vector
	LDR	R0, [R0]
	MOV	R0, R0, LSR #16
	
	LDR	R1, =IRQ_Table			; Get the irq process procedure address
	ADD	R1, R1, R0, LSL #2
	LDR	R0, [R1]
	
	STR	R0, [SP, #8]
	LDMFD	SP!, {R0, R1, PC}
	
	END