fpga_gpio_test.c

ADI blackfin processor BF527 Ezkti test driver

////////////////////////////////////////////////////////////////////////////
//
//  Program to check the functionality of programmable flags on the FPGA EZ-Extender
//
//
//    - PRD
//

#include <cdefBF537.h>
#include <ccblkfn.h>

#include "../post_common.h"
#include "../Timer_ISR.h"



//////////////////////////////////////////////////////////////////////////////
//
// COMMON DEFINES
//
//////////////////////////////////////////////////////////////////////////////


//////////////////////////////////////////////////////////////////////////////
//
// function prototypes
//
//////////////////////////////////////////////////////////////////////////////
void FPGA_Init_GPIO(void);
int TEST_FPGA_GPIO(void);


//////////////////////////////////////////////////////////////////////////////
//
// stand alone test jig
//
//////////////////////////////////////////////////////////////////////////////
#ifdef _STANDALONE_ // use this to run standalone tests
int main(void)
{
	int bPassed = 0;
	
	//InitPLL();
	
	bPassed = TEST_FPGA_GPIO();
			
	
	
	return 0;
}
#endif //#ifdef _STANDALONE_

//--------------------------------------------------------------------------//
// Function:	FPGA_Init_GPIO												//
//																			//
// Parameters:	None														//
//																			//
// Return:		None														//
//																			//
// Description:	This function configures the programmable flags for testing
//--------------------------------------------------------------------------//
void FPGA_Init_GPIO(void)
{
#if (__SILICON_REVISION__ < 0x0001) // Workaround silicon anomaly 05000212
		volatile int temp;
	    temp = *pPORT_MUX; //--possibly anomaly 05000157?
	    ssync();
	    *pPORT_MUX = 0x0e00;
	    ssync();
#endif
		*pPORT_MUX = 0x0e00;
	    ssync();	

	    *pPORTG_FER = 0x0000;	// set portG to GPIO mode
	    *pPORTH_FER = 0x0000;   // set portH to GPIO mode
	    
	    // Set the GPIO direction: 0 = input, 1 = output
	    
	    // PORTG: we will only test PG0-7 as the rest are tested in the SPORT test
	    *pPORTGIO_DIR		= 0x000F;	// PG7-4 as input, PG3-0 as output
		*pPORTGIO_INEN      = 0x00F0;   // enable PG7-4 as inputs
		*pPORTGIO_CLEAR		= 0xFFFF;	// clear the port
		
		
		// PORTH: we will only test PH0-5, The other are used by Ethernet on the EZ-KIT
		*pPORTHIO_DIR		= 0x0007;	// PH5-3 as output
		*pPORTHIO_INEN      = 0x0038;   // enable PH2-0 as inputs
		*pPORTHIO_CLEAR		= 0xFFFF;	// clear the port
		
		ssync();		
		// PORTJ is not tested here as it has no GPIO capabilities
}

void FPGA_Disable_GPIO(void)
{
	*pPORTGIO_DIR		= 0x0000;
	*pPORTGIO_INEN      = 0x0000;
	*pPORTHIO_DIR		= 0x0000;
	*pPORTHIO_INEN      = 0x0000;
}




//////////////////////////////////////////////////////////////////////////////
// int TEST_FPGA_GPIO(void)
// 
// PURPOSE:		Test the programmable flags
//////////////////////////////////////////////////////////////////////////////
int TEST_FPGA_GPIO(void)
{
	int bError = 1; 	// returning 1 indicates a pass, anything else is a fail
	
	FPGA_Init_GPIO();
		
	// test PORTG
	Delay(1);
	if (*pPORTGIO != 0x0000)
		bError = 0;
	
	*pPORTGIO_SET = 0x000F;
	Delay(1);
	if (*pPORTGIO != 0x00FF)
		bError = 0;
		
	*pPORTGIO_CLEAR = 0x000F;
	Delay(1);
	if (*pPORTGIO != 0x0000)
		bError = 0;
	
	*pPORTGIO_SET = 0x0005;
	Delay(1);
	if (*pPORTGIO != 0x0055)
		bError = 0;
	
	*pPORTGIO_CLEAR = 0x0005;
	Delay(1);
	if (*pPORTGIO != 0x0000)
		bError = 0;
	
	*pPORTGIO_SET = 0x000A;
	Delay(1);
	if (*pPORTGIO != 0x00AA)
		bError = 0;
	
	*pPORTGIO_CLEAR = 0x000A;
	Delay(1);
	if (*pPORTGIO != 0x0000)
		bError = 0;
		
	// test PORTH
	if (*pPORTHIO != 0x0000)
		bError = 0;
	
	*pPORTHIO_SET = 0x0007;
	Delay(1);
	if ( ((*pPORTHIO) & 0x3F) != 0x003F )
		bError = 0;
	
	*pPORTHIO_CLEAR = 0x0007;
	Delay(1);
	if (*pPORTHIO != 0x0000)
		bError = 0;
	
	*pPORTHIO_SET = 0x0005;
	Delay(1);
	if ( ((*pPORTHIO) & 0x3F) != 0x002D )
		bError = 0;
	
	*pPORTHIO_CLEAR = 0x0005;
	Delay(1);
	if (*pPORTHIO != 0x0000)
		bError = 0;
	
	*pPORTHIO_SET = 0x0002;
	Delay(1);
	if ( ((*pPORTHIO) & 0x3F) != 0x0012 )
		bError = 0;
	
	*pPORTHIO_CLEAR = 0x002;
	Delay(1);
	if (*pPORTHIO != 0x0000)
		bError = 0;
		
	FPGA_Disable_GPIO();
		
	return bError;
}