fpga_sports_test.c

ADI blackfin processor BF527 Ezkti test driver

////////////////////////////////////////////////////////////////////////////
//
//  Program to check the functionality of the SPORTs via use of the FPGA EZ-Extender
//
//
//    - PRD
//

#include <sys\exception.h>
#include <cdefBF537.h>
#include <ccblkfn.h>

#include "../Timer_ISR.h"



//////////////////////////////////////////////////////////////////////////////
//
// COMMON DEFINES
//
//////////////////////////////////////////////////////////////////////////////




//////////////////////////////////////////////////////////////////////////////
//
// function prototypes
//
//////////////////////////////////////////////////////////////////////////////
EX_INTERRUPT_HANDLER(SPORT0RX_ISR);
EX_INTERRUPT_HANDLER(SPORT0TX_ISR);
EX_INTERRUPT_HANDLER(SPORT1RX_ISR);
EX_INTERRUPT_HANDLER(SPORT1TX_ISR);
int TEST_FPGA_SPORTS(void);


volatile int sp0txCnt = 0;
volatile int sp0rxCnt = 0;
volatile int sp1txCnt = 0;
volatile int sp1rxCnt = 0;

volatile int sp0rxErr = 0;	// 0 = no error, 1 = error
volatile int sp1rxErr = 0;

#define SPORT_BLOCK_SIZE	0x100000  // 4MB

// these buffers will only hold the last 16 data elements that were transfered
volatile int bufSport0RxPrimaryOnly[16];
volatile int bufSport0RxPriSec[16];

volatile int bufSport1RxPrimaryOnly[16];
volatile int bufSport1RxPriSec[16];

volatile int *bufSport0Rx;
volatile int *bufSport1Rx;


//////////////////////////////////////////////////////////////////////////////
//
// stand alone test jig
//
//////////////////////////////////////////////////////////////////////////////
#ifdef _STANDALONE_ // use this to run standalone tests
int main(void)
{
	int bPassed = 0;
	
	bPassed = TEST_FPGA_SPORTS();
		
	return 0;
}
#endif //#ifdef _STANDALONE_


EX_INTERRUPT_HANDLER(SPORT0RX_ISR)
{
	if (sp0rxCnt < SPORT_BLOCK_SIZE)
	{
		bufSport0Rx[sp0rxCnt % 16] = *pSPORT0_RX;
		if (bufSport0Rx[sp0rxCnt % 16] != sp0rxCnt)
		{
			sp0rxErr = 1;
			*pSPORT1_TCR1 &= ~TSPEN;
			*pSPORT0_RCR1 &= ~RSPEN;
		}
		else
		{
			++sp0rxCnt;
		}
	}
	else
	{
		*pSPORT1_TCR1 &= ~TSPEN;
		*pSPORT0_RCR1 &= ~RSPEN;
	}
}

EX_INTERRUPT_HANDLER(SPORT0TX_ISR)
{
	*pSPORT0_TX = sp0txCnt;
	++sp0txCnt;	
}

EX_INTERRUPT_HANDLER(SPORT1RX_ISR)
{
	if (sp1rxCnt < SPORT_BLOCK_SIZE)
	{
		bufSport1Rx[sp1rxCnt % 16] = *pSPORT1_RX;
		if (bufSport1Rx[sp1rxCnt % 16] != sp1rxCnt)
		{
			sp1rxErr = 1;
			*pSPORT0_TCR1 &= ~TSPEN;
			*pSPORT1_RCR1 &= ~RSPEN;
		}
		else
		{
			++sp1rxCnt;
		}
	}
	else
	{
		*pSPORT0_TCR1 &= ~TSPEN;
		*pSPORT1_RCR1 &= ~RSPEN;
	}
}

EX_INTERRUPT_HANDLER(SPORT1TX_ISR)
{
	*pSPORT1_TX = sp1txCnt;
	++sp1txCnt;
}

//////////////////////////////////////////////////////////////////////////////
// int TEST_FPGA_SPORTS(void)
// 
// PURPOSE:		Test the SPORTs by routing them through the FPGA
//////////////////////////////////////////////////////////////////////////////
int TEST_FPGA_SPORTS(void)
{
	int bError = 1; 	// returning 1 indicates a pass, anything else is a fail
	
	unsigned int index = SetTimeout(10*120000000/TIMEOUT_PERIOD);	// about 10 sec @ 120MHz SCLK (1024 is the period of timer0)
	if (index != 0xffffffff)
	{
			
		// set up PORTG and PORTJ as SPORTs
	#if (__SILICON_REVISION__ < 0x0001) // Workaround silicon anomaly 05000212
		volatile int temp;
	    temp = *pPORT_MUX; //--possibly anomaly 05000157?
	    ssync();
	    *pPORT_MUX = 0x0e00;
	    ssync();
	#endif
		*pPORT_MUX = 0x0e00;
	    ssync();
	
		// configure PORTG as peripheral NOT GPIO
		*pPORTG_FER = 0xff00;
				
		// setup the interrupt handlers
		*pSIC_IAR0 = 0x210fffff;
		*pSIC_IAR1 = 0xfffffff3;
		
		register_handler(ik_ivg7,  SPORT0RX_ISR);
		register_handler(ik_ivg8,  SPORT0TX_ISR);
		register_handler(ik_ivg9,  SPORT1RX_ISR);
		register_handler(ik_ivg10, SPORT1TX_ISR);
		
		// enable SPORT0/1 RX/TX interrupts
		*pSIC_IMASK |= IRQ_DMA3 | IRQ_DMA4 | IRQ_DMA5 | IRQ_DMA6;
			
		
		/////////////////////////////////////	
		// setup SPORT0 -> SPORT1 transfer (Primary ONLY)
		/////////////////////////////////////
		sp0txCnt = 0;
		sp1rxCnt = 0;
		bufSport1Rx = bufSport1RxPrimaryOnly;
		
		*pSPORT0_TCR1 = 0;	// make sure the port is disabled
		*pSPORT0_TCR1 = LTFS | TFSR | ITFS | ITCLK;
		*pSPORT0_TCR2 = 31;
		*pSPORT0_TFSDIV = 31;
			
		*pSPORT1_RCR1 = 0;	// make sure the port is disabled
		*pSPORT1_RCR1 = LRFS | RFSR;
		*pSPORT1_RCR2 = 31;	
		*pSPORT1_RFSDIV = 31;
		
		// enable the ports
		*pSPORT1_RCR1 |= RSPEN;
		*pSPORT0_TCR1 |= TSPEN;
			
		// wait for the data to be received or an error
		while ((sp1rxCnt < SPORT_BLOCK_SIZE) && (sp1rxErr == 0))
		{
			if (IsTimedout(index))
			{
				sp1rxErr = 1;
				bError = 0;
				break;
			}
		}
			
		// disable the ports
		*pSPORT1_RCR1 &= ~RSPEN;
		*pSPORT0_TCR1 &= ~TSPEN;
		
		if (sp1rxErr)
		{
			bError = 0;
			return bError;
		}
		
		
		/////////////////////////////////////	
		// setup SPORT0 -> SPORT1 transfer (Primary and Secondary)
		/////////////////////////////////////
		sp0txCnt = 0;
		sp1rxCnt = 0;
		bufSport1Rx = bufSport1RxPriSec;
		
		*pSPORT0_TCR1 = 0;	// make sure the port is disabled
		*pSPORT0_TCR1 = LTFS | TFSR | ITFS | ITCLK;
		*pSPORT0_TCR2 = TXSE | 31;
		*pSPORT0_TFSDIV = 31;
		*pSPORT0_TCLKDIV = 1;
		
		*pSPORT1_RCR1 = 0;	// make sure the port is disabled
		*pSPORT1_RCR1 = LRFS | RFSR;
		*pSPORT1_RCR2 = RXSE | 31;	
		*pSPORT1_RFSDIV = 31;
		
		// enable the ports
		*pSPORT1_RCR1 |= RSPEN;
		*pSPORT0_TCR1 |= TSPEN;
			
		// wait for the data to be received or an error
		while ((sp1rxCnt < SPORT_BLOCK_SIZE) && (sp1rxErr == 0))
		{
			if (IsTimedout(index))
			{
				sp1rxErr = 1;
				bError = 0;
				break;
			}
		}
			
		// disable the ports
		*pSPORT1_RCR1 &= ~RSPEN;
		*pSPORT0_TCR1 &= ~TSPEN;
		
		if (sp1rxErr)
		{
			bError = 0;
			return bError;
		}
			
		
		/////////////////////////////////////	
		// setup SPORT1 -> SPORT0 transfer (Primary ONLY)
		/////////////////////////////////////
		sp1txCnt = 0;
		sp0rxCnt = 0;
		bufSport0Rx = bufSport0RxPrimaryOnly;
		
		*pSPORT1_TCR1 = 0;	// make sure the port is disabled
		*pSPORT1_TCR1 = LTFS | TFSR | ITFS | ITCLK;
		*pSPORT1_TCR2 = 31;
		*pSPORT1_TFSDIV = 31;
		
		*pSPORT0_RCR1 = 0;	// make sure the port is disabled
		*pSPORT0_RCR1 = LRFS | RFSR;
		*pSPORT0_RCR2 = 31;	
		*pSPORT0_RFSDIV = 31;
		
		// enable the ports
		*pSPORT0_RCR1 |= RSPEN;
		*pSPORT1_TCR1 |= TSPEN;
			
		// wait for the data to be received or an error
		while (sp0rxCnt < SPORT_BLOCK_SIZE && sp0rxErr == 0)
		{
			if (IsTimedout(index))
			{
				sp0rxErr = 1;
				bError = 0;
				break;
			}
		}
			
		// disable the ports
		*pSPORT0_RCR1 &= ~RSPEN;
		*pSPORT1_TCR1 &= ~TSPEN;
		
		if (sp0rxErr)
		{
			bError = 0;
			return bError;
		}
		
		
		/////////////////////////////////////	
		// setup SPORT1 -> SPORT0 transfer (Primary and Secondary)
		/////////////////////////////////////
		sp1txCnt = 0;
		sp0rxCnt = 0;
		bufSport0Rx = bufSport0RxPriSec;
		
		*pSPORT1_TCR1 = 0;	// make sure the port is disabled
		*pSPORT1_TCR1 = LTFS | TFSR | ITFS | ITCLK;
		*pSPORT1_TCR2 = TXSE | 31;
		*pSPORT1_TFSDIV = 31;
		*pSPORT1_TCLKDIV = 1;
		
		*pSPORT0_RCR1 = 0;	// make sure the port is disabled
		*pSPORT0_RCR1 = LRFS | RFSR;
		*pSPORT0_RCR2 = RXSE | 31;	
		*pSPORT0_RFSDIV = 31;
		
		// enable the ports
		*pSPORT0_RCR1 |= RSPEN;
		*pSPORT1_TCR1 |= TSPEN;
			
		// wait for the data to be received or an error
		while (sp0rxCnt < SPORT_BLOCK_SIZE && sp0rxErr == 0)
		{
			if (IsTimedout(index))
			{
				sp0rxErr = 1;
				bError = 0;
				break;
			}
		}
			
		// disable the ports
		*pSPORT0_RCR1 &= ~RSPEN;
		*pSPORT1_TCR1 &= ~TSPEN;
		
		if (sp0rxErr)
		{
			bError = 0;
			return bError;
		}
	
		ClearTimeout(index);
	}
	else
	{
		bError = 0;
	}
		
	// clean-up, keep TIMER0 enabled though
	*pSIC_IAR0 = 0xffffffff;
	*pSIC_IAR1 = 0xffffffff;
	*pSIC_IAR2 = 0xffff4fff;
	*pSIC_IMASK = IRQ_TIMER0;
		    	
	return bError;	// 0 = error, 1 = pass
}