fpga_memory_test.c

ADI blackfin processor BF527 Ezkti test driver

////////////////////////////////////////////////////////////////////////////
//
//  Program to check the functionality of SRAM on the FPGA EZ-Extender
//
//
//    - PRD
//

#include <cdefBF537.h>
#include <ccblkfn.h>

#include "../Timer_ISR.h"



//////////////////////////////////////////////////////////////////////////////
//
// COMMON DEFINES
//
//////////////////////////////////////////////////////////////////////////////
#define SRAM_START  0x20200000	// start address of SRAM (uses /AMS2, SW6.3 set to OFF)
#define SRAM_SIZE	0x00080000	// 512k x 32-bits



//////////////////////////////////////////////////////////////////////////////
//
// function prototypes
//
//////////////////////////////////////////////////////////////////////////////
void FPGA_Init_MemTest(void);
int TEST_FPGA_MEMORY(void);



//////////////////////////////////////////////////////////////////////////////
//
// stand alone test jig
//
//////////////////////////////////////////////////////////////////////////////
#ifdef _STANDALONE_ // use this to run standalone tests
int main(void)
{
	int bPassed = 0;
	
	//InitPLL();
	
	bPassed = TEST_FPGA_MEMORY();
			
	
	
	return 0;
}
#endif //#ifdef _STANDALONE_

//--------------------------------------------------------------------------//
// Function:	FPGA_Init_MemTest											//
//																			//
// Parameters:	None														//
//																			//
// Return:		None														//
//																			//
// Description:	This function configures the EBIU to allow access to
//              the FPGA as a memory mapped peripheral
//--------------------------------------------------------------------------//
void FPGA_Init_MemTest(void)
{
	// the FPGA is mapped into memory at address 0x20200000 by setting 
	// SW6.3 to the OFF position (/AMS2)
	
	// Initalize EBIU control registers to enable all banks	
	*pEBIU_AMBCTL1 = 0xFFFFFF02;
	ssync();
	
	*pEBIU_AMGCTL = 0x00FE;
	ssync();
	
	// PG13 is used as bank select for the SRAM
	// PG13 = 0 accesses lower bank 15:0
	// PG13 = 1 accesses upper bank 31:16
	*pPORTG_FER = 0x0000;		// put PG0 - PG15 in GPIO mode
	// Set the GPIO direction: 0 = input, 1 = output
	*pPORTGIO_DIR		= 0x2000;	// PG13 = ouput
	*pPORTGIO_CLEAR		= 0x2000;	// PG13 = 0
}

//////////////////////////////////////////////////////////////////////////////
// int TEST_FPGA_MEMORY(void)
// 
// PURPOSE:		Test the SRAM by making core access to it via the FPGA
//////////////////////////////////////////////////////////////////////////////
int TEST_FPGA_MEMORY(void)
{
	
	volatile unsigned int *pDst;
	int nIndex = 0;
	int bError = 1; 	// returning 1 indicates a pass, anything else is a fail
	int nTests;
	
	FPGA_Init_MemTest();	
		
	for(nTests = 0; nTests < 2; ++nTests)
	{
		if (nTests == 0)
			*pPORTGIO_CLEAR	= 0x2000;	// PG13 = 0 : Test BANK0
		else
			*pPORTGIO_SET	= 0x2000;	// PG13 = 1 : Test BANK1
		
		// write incrementing values to each SRAM location
		for(nIndex = 0, pDst = (unsigned int *)SRAM_START; pDst < (unsigned int *)(SRAM_START + SRAM_SIZE); pDst++, nIndex++ )
		{
			*pDst = nIndex;
			ssync();
		}
		
		// verify incrementing values
		for(nIndex = 0, pDst = (unsigned int *)SRAM_START; pDst < (unsigned int *)(SRAM_START + SRAM_SIZE); pDst++, nIndex++ )
		{
			if( nIndex != *pDst )
			{
				bError = 0;
				break;
			}
		}
		
		// write all FFFF's 
		for(nIndex = 0xFFFFFFFF, pDst = (unsigned int *)SRAM_START; pDst < (unsigned int *)(SRAM_START + SRAM_SIZE); pDst++ )
		{
			*pDst = nIndex;
		}
		
		// verify all FFFF's 
		for(nIndex = 0xFFFFFFFF, pDst = (unsigned int *)SRAM_START; pDst < (unsigned int *)(SRAM_START + SRAM_SIZE); pDst++ )
		{
			if( nIndex != *pDst )
			{
				bError = 0;
				break;
			}
		}
		
		// write all AAAA's 
		for(nIndex = 0xAAAAAAAA, pDst = (unsigned int *)SRAM_START; pDst < (unsigned int *)(SRAM_START + SRAM_SIZE); pDst++ )
		{
			*pDst = nIndex;
		}
		
		// verify all AAAA's 
		for(nIndex = 0xAAAAAAAA, pDst = (unsigned int *)SRAM_START; pDst < (unsigned int *)(SRAM_START + SRAM_SIZE); pDst++ )
		{
			if( nIndex != *pDst )
			{
				bError = 0;
				break;
			}
		}
			
		// write all 5555's 
		for(nIndex = 0x55555555, pDst = (unsigned int *)SRAM_START; pDst < (unsigned int *)(SRAM_START + SRAM_SIZE); pDst++ )
		{
			*pDst = nIndex;
		}
		
		// verify all 5555's 
		for(nIndex = 0x55555555, pDst = (unsigned int *)SRAM_START; pDst < (unsigned int *)(SRAM_START + SRAM_SIZE); pDst++ )
		{
			if( nIndex != *pDst )
			{
				bError = 0;
				break;
			}
		}
	}
	
	int wrBank0 = 0x1234, rdBank0;
	int wrBank1 = 0x5678, rdBank1;
	pDst = (unsigned int *)SRAM_START;
	// write to bank0
	*pPORTGIO_CLEAR	= 0x2000;	// PG13 = 0 : Test BANK0	
	*pDst = wrBank0;
	Delay(1);
	rdBank0 = *pDst;
	if (rdBank0 != wrBank0)
		bError = 0;
	// write to bank1
	*pPORTGIO_SET	= 0x2000;	// PG13 = 1 : Test BANK1	
	*pDst = wrBank1;
	Delay(1);
	rdBank1 = *pDst;
	if (rdBank1 != wrBank1)
		bError = 0;
	
	// now check that the bank selection is really working
	// read from bank0 and make sure we don't match the bank1 value
	*pPORTGIO_CLEAR	= 0x2000;	// PG13 = 0 : Test BANK0	
	rdBank0 = *pDst;
	if (rdBank0 == wrBank1)
		bError = 0;
	// read from bank1 and make sure we don't match the bank0 value
	*pPORTGIO_SET	= 0x2000;	// PG13 = 1 : Test BANK1	
	rdBank1 = *pDst;
	if (rdBank1 == wrBank0)
		bError = 0;
	    

	return bError;
}