📄 at91sam9261_inc.h
字号:
#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
// *****************************************************************************
// *** Register offset in AT91S_PIO structure ***
#define PIO_PER ( 0) // PIO Enable Register
#define PIO_PDR ( 4) // PIO Disable Register
#define PIO_PSR ( 8) // PIO Status Register
#define PIO_OER (16) // Output Enable Register
#define PIO_ODR (20) // Output Disable Registerr
#define PIO_OSR (24) // Output Status Register
#define PIO_IFER (32) // Input Filter Enable Register
#define PIO_IFDR (36) // Input Filter Disable Register
#define PIO_IFSR (40) // Input Filter Status Register
#define PIO_SODR (48) // Set Output Data Register
#define PIO_CODR (52) // Clear Output Data Register
#define PIO_ODSR (56) // Output Data Status Register
#define PIO_PDSR (60) // Pin Data Status Register
#define PIO_IER (64) // Interrupt Enable Register
#define PIO_IDR (68) // Interrupt Disable Register
#define PIO_IMR (72) // Interrupt Mask Register
#define PIO_ISR (76) // Interrupt Status Register
#define PIO_MDER (80) // Multi-driver Enable Register
#define PIO_MDDR (84) // Multi-driver Disable Register
#define PIO_MDSR (88) // Multi-driver Status Register
#define PIO_PPUDR (96) // Pull-up Disable Register
#define PIO_PPUER (100) // Pull-up Enable Register
#define PIO_PPUSR (104) // Pull-up Status Register
#define PIO_ASR (112) // Select A Register
#define PIO_BSR (116) // Select B Register
#define PIO_ABSR (120) // AB Select Status Register
#define PIO_OWER (160) // Output Write Enable Register
#define PIO_OWDR (164) // Output Write Disable Register
#define PIO_OWSR (168) // Output Write Status Register
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Clock Generator Controler
// *****************************************************************************
// *** Register offset in AT91S_CKGR structure ***
#define CKGR_MOR ( 0) // Main Oscillator Register
#define CKGR_MCFR ( 4) // Main Clock Frequency Register
#define CKGR_PLLAR ( 8) // PLL A Register
#define CKGR_PLLBR (12) // PLL B Register
// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register --------
#define AT91C_CKGR_DIVA (0xFF << 0) // (CKGR) Divider A Selected
#define AT91C_CKGR_DIVA_0 (0x0) // (CKGR) Divider A output is 0
#define AT91C_CKGR_DIVA_BYPASS (0x1) // (CKGR) Divider A is bypassed
#define AT91C_CKGR_PLLACOUNT (0x3F << 8) // (CKGR) PLL A Counter
#define AT91C_CKGR_OUTA (0x3 << 14) // (CKGR) PLL A Output Frequency Range
#define AT91C_CKGR_OUTA_0 (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet
#define AT91C_CKGR_OUTA_1 (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet
#define AT91C_CKGR_OUTA_2 (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet
#define AT91C_CKGR_OUTA_3 (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet
#define AT91C_CKGR_MULA (0x7FF << 16) // (CKGR) PLL A Multiplier
#define AT91C_CKGR_SRCA (0x1 << 29) // (CKGR)
// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register --------
#define AT91C_CKGR_DIVB (0xFF << 0) // (CKGR) Divider B Selected
#define AT91C_CKGR_DIVB_0 (0x0) // (CKGR) Divider B output is 0
#define AT91C_CKGR_DIVB_BYPASS (0x1) // (CKGR) Divider B is bypassed
#define AT91C_CKGR_PLLBCOUNT (0x3F << 8) // (CKGR) PLL B Counter
#define AT91C_CKGR_OUTB (0x3 << 14) // (CKGR) PLL B Output Frequency Range
#define AT91C_CKGR_OUTB_0 (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet
#define AT91C_CKGR_OUTB_1 (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet
#define AT91C_CKGR_OUTB_2 (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet
#define AT91C_CKGR_OUTB_3 (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet
#define AT91C_CKGR_MULB (0x7FF << 16) // (CKGR) PLL B Multiplier
#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Power Management Controler
// *****************************************************************************
// *** Register offset in AT91S_PMC structure ***
#define PMC_SCER ( 0) // System Clock Enable Register
#define PMC_SCDR ( 4) // System Clock Disable Register
#define PMC_SCSR ( 8) // System Clock Status Register
#define PMC_PCER (16) // Peripheral Clock Enable Register
#define PMC_PCDR (20) // Peripheral Clock Disable Register
#define PMC_PCSR (24) // Peripheral Clock Status Register
#define PMC_MOR (32) // Main Oscillator Register
#define PMC_MCFR (36) // Main Clock Frequency Register
#define PMC_PLLAR (40) // PLL A Register
#define PMC_PLLBR (44) // PLL B Register
#define PMC_MCKR (48) // Master Clock Register
#define PMC_PCKR (64) // Programmable Clock Register
#define PMC_IER (96) // Interrupt Enable Register
#define PMC_IDR (100) // Interrupt Disable Register
#define PMC_SR (104) // Status Register
#define PMC_IMR (108) // Interrupt Mask Register
// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
#define AT91C_PMC_UHP (0x1 << 6) // (PMC) USB Host Port Clock
#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output
#define AT91C_PMC_HCK0 (0x1 << 16) // (PMC) AHB UHP Clock Output
#define AT91C_PMC_HCK1 (0x1 << 17) // (PMC) AHB LCDC Clock Output
// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
// -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register --------
// -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register --------
// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
#define AT91C_PMC_CSS_PLLA_CLK (0x2) // (PMC) Clock from PLL A is selected
#define AT91C_PMC_CSS_PLLB_CLK (0x3) // (PMC) Clock from PLL B is selected
#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
#define AT91C_PMC_MDIV (0x3 << 8) // (PMC) Master Clock Division
#define AT91C_PMC_MDIV_1 (0x0 << 8) // (PMC) The master clock and the processor clock are the same
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -