📄 at91sam9261.h
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#define AT91C_SMC_NWECYCLE ((unsigned int) 0x1FF << 0) // (SMC) Total Write Cycle Length
#define AT91C_SMC_NRDCYCLE ((unsigned int) 0x1FF << 16) // (SMC) Total Read Cycle Length
// -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x --------
#define AT91C_SMC_READMODE ((unsigned int) 0x1 << 0) // (SMC) Read Mode
#define AT91C_SMC_WRITEMODE ((unsigned int) 0x1 << 1) // (SMC) Write Mode
#define AT91C_SMC_NWAITM ((unsigned int) 0x3 << 5) // (SMC) NWAIT Mode
#define AT91C_SMC_NWAITM_NWAIT_DISABLE ((unsigned int) 0x0 << 5) // (SMC) External NWAIT disabled.
#define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN ((unsigned int) 0x2 << 5) // (SMC) External NWAIT enabled in frozen mode.
#define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY ((unsigned int) 0x3 << 5) // (SMC) External NWAIT enabled in ready mode.
#define AT91C_SMC_BAT ((unsigned int) 0x1 << 8) // (SMC) Byte Access Type
#define AT91C_SMC_BAT_BYTE_SELECT ((unsigned int) 0x0 << 8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
#define AT91C_SMC_BAT_BYTE_WRITE ((unsigned int) 0x1 << 8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.
#define AT91C_SMC_DBW ((unsigned int) 0x3 << 12) // (SMC) Data Bus Width
#define AT91C_SMC_DBW_WIDTH_EIGTH_BITS ((unsigned int) 0x0 << 12) // (SMC) 8 bits.
#define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS ((unsigned int) 0x1 << 12) // (SMC) 16 bits.
#define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS ((unsigned int) 0x2 << 12) // (SMC) 32 bits.
#define AT91C_SMC_TDF ((unsigned int) 0xF << 16) // (SMC) Data Float Time.
#define AT91C_SMC_TDFEN ((unsigned int) 0x1 << 20) // (SMC) TDF Enabled.
#define AT91C_SMC_PMEN ((unsigned int) 0x1 << 24) // (SMC) Page Mode Enabled.
#define AT91C_SMC_PS ((unsigned int) 0x3 << 28) // (SMC) Page Size
#define AT91C_SMC_PS_SIZE_FOUR_BYTES ((unsigned int) 0x0 << 28) // (SMC) 4 bytes.
#define AT91C_SMC_PS_SIZE_EIGHT_BYTES ((unsigned int) 0x1 << 28) // (SMC) 8 bytes.
#define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES ((unsigned int) 0x2 << 28) // (SMC) 16 bytes.
#define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES ((unsigned int) 0x3 << 28) // (SMC) 32 bytes.
// -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x --------
// -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x --------
// -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x --------
// -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x --------
// -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR AHB Matrix Interface
// *****************************************************************************
typedef struct _AT91S_MATRIX {
AT91_REG MATRIX_MCFG; // Master Configuration Register
AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0
AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1
AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2
AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3
AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4
AT91_REG Reserved0[3]; //
AT91_REG MATRIX_TCMR; // Slave 0 Special Function Register
AT91_REG Reserved1[2]; //
AT91_REG MATRIX_EBICSA; // Slave 3 Special Function Register
AT91_REG MATRIX_USBPCR; // Slave 4 Special Function Register
AT91_REG Reserved2[3]; //
AT91_REG MATRIX_VERSION; // Version Register
} AT91S_MATRIX, *AT91PS_MATRIX;
// -------- MATRIX_MCFG : (MATRIX Offset: 0x0) Master Configuration Register --------
#define AT91C_MATRIX_RCA926I ((unsigned int) 0x1 << 0) // (MATRIX) Remap Command for ARM926EJ-S Instruction Master
#define AT91C_MATRIX_RCA926D ((unsigned int) 0x1 << 1) // (MATRIX) Remap Command for ARM926EJ-S Data Master
// -------- MATRIX_SCFG0 : (MATRIX Offset: 0x4) Slave Configuration Register 0 --------
#define AT91C_MATRIX_SLOT_CYCLE ((unsigned int) 0xFF << 0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst
#define AT91C_MATRIX_DEFMSTR_TYPE ((unsigned int) 0x3 << 16) // (MATRIX) Default Master Type
#define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR ((unsigned int) 0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
#define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR ((unsigned int) 0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
#define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR ((unsigned int) 0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
#define AT91C_MATRIX_FIXED_DEFMSTR0 ((unsigned int) 0x7 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I ((unsigned int) 0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D ((unsigned int) 0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_HPDC3 ((unsigned int) 0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_LCDC ((unsigned int) 0x3 << 18) // (MATRIX) LCDC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR0_UHP ((unsigned int) 0x4 << 18) // (MATRIX) UHP Master is Default Master
// -------- MATRIX_SCFG1 : (MATRIX Offset: 0x8) Slave Configuration Register 1 --------
#define AT91C_MATRIX_FIXED_DEFMSTR1 ((unsigned int) 0x7 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I ((unsigned int) 0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D ((unsigned int) 0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_HPDC3 ((unsigned int) 0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_LCDC ((unsigned int) 0x3 << 18) // (MATRIX) LCDC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR1_UHP ((unsigned int) 0x4 << 18) // (MATRIX) UHP Master is Default Master
// -------- MATRIX_SCFG2 : (MATRIX Offset: 0xc) Slave Configuration Register 2 --------
#define AT91C_MATRIX_FIXED_DEFMSTR2 ((unsigned int) 0x1 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I ((unsigned int) 0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D ((unsigned int) 0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
// -------- MATRIX_SCFG3 : (MATRIX Offset: 0x10) Slave Configuration Register 3 --------
#define AT91C_MATRIX_FIXED_DEFMSTR3 ((unsigned int) 0x7 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I ((unsigned int) 0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D ((unsigned int) 0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_HPDC3 ((unsigned int) 0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_LCDC ((unsigned int) 0x3 << 18) // (MATRIX) LCDC Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR3_UHP ((unsigned int) 0x4 << 18) // (MATRIX) UHP Master is Default Master
// -------- MATRIX_SCFG4 : (MATRIX Offset: 0x14) Slave Configuration Register 4 --------
#define AT91C_MATRIX_FIXED_DEFMSTR4 ((unsigned int) 0x3 << 18) // (MATRIX) Fixed Index of Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I ((unsigned int) 0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D ((unsigned int) 0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
#define AT91C_MATRIX_FIXED_DEFMSTR4_HPDC3 ((unsigned int) 0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
// -------- MATRIX_TCMR : (MATRIX Offset: 0x24) TCM (Slave 0) Special Function Register --------
#define AT91C_MATRIX_ITCM_SIZE ((unsigned int) 0xF << 0) // (MATRIX) Size of ITCM enabled memory block
#define AT91C_MATRIX_ITCM_SIZE_0KB ((unsigned int) 0x0) // (MATRIX) 0 KB (No ITCM Memory)
#define AT91C_MATRIX_ITCM_SIZE_16KB ((unsigned int) 0x5) // (MATRIX) 16 KB
#define AT91C_MATRIX_ITCM_SIZE_32KB ((unsigned int) 0x6) // (MATRIX) 32 KB
#define AT91C_MATRIX_ITCM_SIZE_64KB ((unsigned int) 0x7) // (MATRIX) 64 KB
#define AT91C_MATRIX_DTCM_SIZE ((unsigned int) 0xF << 4) // (MATRIX) Size of DTCM enabled memory block
#define AT91C_MATRIX_DTCM_SIZE_0KB ((unsigned int) 0x0 << 4) // (MATRIX) 0 KB (No DTCM Memory)
#define AT91C_MATRIX_DTCM_SIZE_16KB ((unsigned int) 0x5 << 4) // (MATRIX) 16 KB
#define AT91C_MATRIX_DTCM_SIZE_32KB ((unsigned int) 0x6 << 4) // (MATRIX) 32 KB
#define AT91C_MATRIX_DTCM_SIZE_64KB ((unsigned int) 0x7 << 4) // (MATRIX) 64 KB
// -------- MATRIX_EBICSA : (MATRIX Offset: 0x30) EBI (Slave 3) Special Function Register --------
#define AT91C_MATRIX_CS1A ((unsigned int) 0x1 << 1) // (MATRIX) Chip Select 1 Assignment
#define AT91C_MATRIX_CS1A_SMC ((unsigned int) 0x0 << 1) // (MATRIX) Chip Select 1 is assigned to the Static Memory Controller.
#define AT91C_MATRIX_CS1A_SDRAMC ((unsigned int) 0x1 << 1) // (MATRIX) Chip Select 1 is assigned to the SDRAM Controller.
#define AT91C_MATRIX_CS3A ((unsigned int) 0x1 << 3) // (MATRIX) Chip Select 3 Assignment
#define AT91C_MATRIX_CS3A_SMC ((unsigned int) 0x0 << 3) // (MATRIX) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
#define AT91C_MATRIX_CS3A_SM ((unsigned int) 0x1 << 3) // (MATRIX) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
#define AT91C_MATRIX_CS4A ((unsigned int) 0x1 << 4) // (MATRIX) Chip Select 4 Assignment
#define AT91C_MATRIX_CS4A_SMC ((unsigned int) 0x0 << 4) // (MATRIX) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
#define AT91C_MATRIX_CS4A_CF ((unsigned int) 0x1 << 4) // (MATRIX) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
#define AT91C_MATRIX_CS5A ((unsigned int) 0x1 << 5) // (MATRIX) Chip Select 5 Assignment
#define AT91C_MATRIX_CS5A_SMC ((unsigned int) 0x0 << 5) // (MATRIX) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
#define AT91C_MATRIX_CS5A_CF ((unsigned int) 0x1 << 5) // (MATRIX) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
#define AT91C_MATRIX_DBPUC ((unsigned int) 0x1 << 8) // (MATRIX) Data Bus Pull-up Configuration
// -------- MATRIX_USBPCR : (MATRIX Offset: 0x34) USB Pad Control Register --------
#define AT91C_MATRIX_USBPCR_PUON ((unsigned int) 0x1 << 30) // (MATRIX) PullUp On
#define AT91C_MATRIX_USBPCR_PUIDLE ((unsigned int) 0x1 << 31) // (MATRIX) PullUp Idle
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
// *****************************************************************************
typedef struct _AT91S_AIC {
AT91_REG AIC_SMR[32]; // Source Mode Register
AT91_REG AIC_SVR[32]; // Source Vector Register
AT91_REG AIC_IVR; // IRQ Vector Register
AT91_REG AIC_FVR; // FIQ Vector Register
AT91_REG AIC_ISR; // Interrupt Status Register
AT91_REG AIC_IPR; // Interrupt Pending Register
AT91_REG AIC_IMR; // Interrupt Mask Register
AT91_REG AIC_CISR; // Core Interrupt Status Register
AT91_REG Reserved0[2]; //
AT91_REG AIC_IECR; // Interrupt Enable Command Register
AT91_REG AIC_IDCR; // Interrupt Disable Command Register
AT91_REG AIC_ICCR; // Interrupt Clear Command Register
AT91_REG AIC_ISCR; // Interrupt Set Command Register
AT91_REG AIC_EOICR; // End of Interrupt Command Register
AT91_REG AIC_SPU; // Spurious Vector Register
AT91_REG AIC_DCR; // Debug Control Register (Protect)
AT91_REG Reserved1[1]; //
AT91_REG AIC_FFER; // Fast Forcing Enable Register
AT91_REG AIC_FFDR; // Fast Forcing Disable Register
AT91_REG AIC_FFSR; // Fast Forcing Status Register
} AT91S_AIC, *AT91PS_AIC;
// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
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