📄 at91sam9261.h
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AT91_REG Reserved15[1]; //
AT91_REG PIOA_PPUDR; // Pull-up Disable Register
AT91_REG PIOA_PPUER; // Pull-up Enable Register
AT91_REG PIOA_PPUSR; // Pull-up Status Register
AT91_REG Reserved16[1]; //
AT91_REG PIOA_ASR; // Select A Register
AT91_REG PIOA_BSR; // Select B Register
AT91_REG PIOA_ABSR; // AB Select Status Register
AT91_REG Reserved17[9]; //
AT91_REG PIOA_OWER; // Output Write Enable Register
AT91_REG PIOA_OWDR; // Output Write Disable Register
AT91_REG PIOA_OWSR; // Output Write Status Register
AT91_REG Reserved18[85]; //
AT91_REG PIOB_PER; // PIO Enable Register
AT91_REG PIOB_PDR; // PIO Disable Register
AT91_REG PIOB_PSR; // PIO Status Register
AT91_REG Reserved19[1]; //
AT91_REG PIOB_OER; // Output Enable Register
AT91_REG PIOB_ODR; // Output Disable Registerr
AT91_REG PIOB_OSR; // Output Status Register
AT91_REG Reserved20[1]; //
AT91_REG PIOB_IFER; // Input Filter Enable Register
AT91_REG PIOB_IFDR; // Input Filter Disable Register
AT91_REG PIOB_IFSR; // Input Filter Status Register
AT91_REG Reserved21[1]; //
AT91_REG PIOB_SODR; // Set Output Data Register
AT91_REG PIOB_CODR; // Clear Output Data Register
AT91_REG PIOB_ODSR; // Output Data Status Register
AT91_REG PIOB_PDSR; // Pin Data Status Register
AT91_REG PIOB_IER; // Interrupt Enable Register
AT91_REG PIOB_IDR; // Interrupt Disable Register
AT91_REG PIOB_IMR; // Interrupt Mask Register
AT91_REG PIOB_ISR; // Interrupt Status Register
AT91_REG PIOB_MDER; // Multi-driver Enable Register
AT91_REG PIOB_MDDR; // Multi-driver Disable Register
AT91_REG PIOB_MDSR; // Multi-driver Status Register
AT91_REG Reserved22[1]; //
AT91_REG PIOB_PPUDR; // Pull-up Disable Register
AT91_REG PIOB_PPUER; // Pull-up Enable Register
AT91_REG PIOB_PPUSR; // Pull-up Status Register
AT91_REG Reserved23[1]; //
AT91_REG PIOB_ASR; // Select A Register
AT91_REG PIOB_BSR; // Select B Register
AT91_REG PIOB_ABSR; // AB Select Status Register
AT91_REG Reserved24[9]; //
AT91_REG PIOB_OWER; // Output Write Enable Register
AT91_REG PIOB_OWDR; // Output Write Disable Register
AT91_REG PIOB_OWSR; // Output Write Status Register
AT91_REG Reserved25[85]; //
AT91_REG PIOC_PER; // PIO Enable Register
AT91_REG PIOC_PDR; // PIO Disable Register
AT91_REG PIOC_PSR; // PIO Status Register
AT91_REG Reserved26[1]; //
AT91_REG PIOC_OER; // Output Enable Register
AT91_REG PIOC_ODR; // Output Disable Registerr
AT91_REG PIOC_OSR; // Output Status Register
AT91_REG Reserved27[1]; //
AT91_REG PIOC_IFER; // Input Filter Enable Register
AT91_REG PIOC_IFDR; // Input Filter Disable Register
AT91_REG PIOC_IFSR; // Input Filter Status Register
AT91_REG Reserved28[1]; //
AT91_REG PIOC_SODR; // Set Output Data Register
AT91_REG PIOC_CODR; // Clear Output Data Register
AT91_REG PIOC_ODSR; // Output Data Status Register
AT91_REG PIOC_PDSR; // Pin Data Status Register
AT91_REG PIOC_IER; // Interrupt Enable Register
AT91_REG PIOC_IDR; // Interrupt Disable Register
AT91_REG PIOC_IMR; // Interrupt Mask Register
AT91_REG PIOC_ISR; // Interrupt Status Register
AT91_REG PIOC_MDER; // Multi-driver Enable Register
AT91_REG PIOC_MDDR; // Multi-driver Disable Register
AT91_REG PIOC_MDSR; // Multi-driver Status Register
AT91_REG Reserved29[1]; //
AT91_REG PIOC_PPUDR; // Pull-up Disable Register
AT91_REG PIOC_PPUER; // Pull-up Enable Register
AT91_REG PIOC_PPUSR; // Pull-up Status Register
AT91_REG Reserved30[1]; //
AT91_REG PIOC_ASR; // Select A Register
AT91_REG PIOC_BSR; // Select B Register
AT91_REG PIOC_ABSR; // AB Select Status Register
AT91_REG Reserved31[9]; //
AT91_REG PIOC_OWER; // Output Write Enable Register
AT91_REG PIOC_OWDR; // Output Write Disable Register
AT91_REG PIOC_OWSR; // Output Write Status Register
AT91_REG Reserved32[213]; //
AT91_REG PMC_SCER; // System Clock Enable Register
AT91_REG PMC_SCDR; // System Clock Disable Register
AT91_REG PMC_SCSR; // System Clock Status Register
AT91_REG Reserved33[1]; //
AT91_REG PMC_PCER; // Peripheral Clock Enable Register
AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
AT91_REG PMC_PCSR; // Peripheral Clock Status Register
AT91_REG Reserved34[1]; //
AT91_REG PMC_MOR; // Main Oscillator Register
AT91_REG PMC_MCFR; // Main Clock Frequency Register
AT91_REG PMC_PLLAR; // PLL A Register
AT91_REG PMC_PLLBR; // PLL B Register
AT91_REG PMC_MCKR; // Master Clock Register
AT91_REG Reserved35[3]; //
AT91_REG PMC_PCKR[8]; // Programmable Clock Register
AT91_REG PMC_IER; // Interrupt Enable Register
AT91_REG PMC_IDR; // Interrupt Disable Register
AT91_REG PMC_SR; // Status Register
AT91_REG PMC_IMR; // Interrupt Mask Register
AT91_REG Reserved36[36]; //
AT91_REG RSTC_RCR; // Reset Control Register
AT91_REG RSTC_RSR; // Reset Status Register
AT91_REG RSTC_RMR; // Reset Mode Register
AT91_REG Reserved37[1]; //
AT91_REG SHDWC_SHCR; // Shut Down Control Register
AT91_REG SHDWC_SHMR; // Shut Down Mode Register
AT91_REG SHDWC_SHSR; // Shut Down Status Register
AT91_REG Reserved38[1]; //
AT91_REG RTTC_RTMR; // Real-time Mode Register
AT91_REG RTTC_RTAR; // Real-time Alarm Register
AT91_REG RTTC_RTVR; // Real-time Value Register
AT91_REG RTTC_RTSR; // Real-time Status Register
AT91_REG PITC_PIMR; // Period Interval Mode Register
AT91_REG PITC_PISR; // Period Interval Status Register
AT91_REG PITC_PIVR; // Period Interval Value Register
AT91_REG PITC_PIIR; // Period Interval Image Register
AT91_REG WDTC_WDCR; // Watchdog Control Register
AT91_REG WDTC_WDMR; // Watchdog Mode Register
AT91_REG WDTC_WDSR; // Watchdog Status Register
AT91_REG Reserved39[1]; //
AT91_REG SYS_GPBR0; // General Purpose Register 0
AT91_REG SYS_GPBR1; // General Purpose Register 1
AT91_REG SYS_GPBR2; // General Purpose Register 2
AT91_REG SYS_GPBR3; // General Purpose Register 3
} AT91S_SYS, *AT91PS_SYS;
// -------- GPBR : (SYS Offset: 0x1350) GPBR General Purpose Register --------
// -------- GPBR : (SYS Offset: 0x1354) GPBR General Purpose Register --------
// -------- GPBR : (SYS Offset: 0x1358) GPBR General Purpose Register --------
// -------- GPBR : (SYS Offset: 0x135c) GPBR General Purpose Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR SDRAM Controller Interface
// *****************************************************************************
typedef struct _AT91S_SDRAMC {
AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register
AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register
AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register
AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register
AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register
AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register
AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register
AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register
AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register
AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register
} AT91S_SDRAMC, *AT91PS_SDRAMC;
// -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register --------
#define AT91C_SDRAMC_MODE ((unsigned int) 0xF << 0) // (SDRAMC) Mode
#define AT91C_SDRAMC_MODE_NORMAL_CMD ((unsigned int) 0x0) // (SDRAMC) Normal Mode
#define AT91C_SDRAMC_MODE_NOP_CMD ((unsigned int) 0x1) // (SDRAMC) Issue a NOP Command at every access
#define AT91C_SDRAMC_MODE_PRCGALL_CMD ((unsigned int) 0x2) // (SDRAMC) Issue a All Banks Precharge Command at every access
#define AT91C_SDRAMC_MODE_LMR_CMD ((unsigned int) 0x3) // (SDRAMC) Issue a Load Mode Register at every access
#define AT91C_SDRAMC_MODE_RFSH_CMD ((unsigned int) 0x4) // (SDRAMC) Issue a Refresh
#define AT91C_SDRAMC_MODE_EXT_LMR_CMD ((unsigned int) 0x5) // (SDRAMC) Issue an Extended Load Mode Register
#define AT91C_SDRAMC_MODE_DEEP_CMD ((unsigned int) 0x6) // (SDRAMC) Enter Deep Power Mode
// -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register --------
#define AT91C_SDRAMC_COUNT ((unsigned int) 0xFFF << 0) // (SDRAMC) Refresh Counter
// -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register --------
#define AT91C_SDRAMC_NC ((unsigned int) 0x3 << 0) // (SDRAMC) Number of Column Bits
#define AT91C_SDRAMC_NC_8 ((unsigned int) 0x0) // (SDRAMC) 8 Bits
#define AT91C_SDRAMC_NC_9 ((unsigned int) 0x1) // (SDRAMC) 9 Bits
#define AT91C_SDRAMC_NC_10 ((unsigned int) 0x2) // (SDRAMC) 10 Bits
#define AT91C_SDRAMC_NC_11 ((unsigned int) 0x3) // (SDRAMC) 11 Bits
#define AT91C_SDRAMC_NR ((unsigned int) 0x3 << 2) // (SDRAMC) Number of Row Bits
#define AT91C_SDRAMC_NR_11 ((unsigned int) 0x0 << 2) // (SDRAMC) 11 Bits
#define AT91C_SDRAMC_NR_12 ((unsigned int) 0x1 << 2) // (SDRAMC) 12 Bits
#define AT91C_SDRAMC_NR_13 ((unsigned int) 0x2 << 2) // (SDRAMC) 13 Bits
#define AT91C_SDRAMC_NB ((unsigned int) 0x1 << 4) // (SDRAMC) Number of Banks
#define AT91C_SDRAMC_NB_2_BANKS ((unsigned int) 0x0 << 4) // (SDRAMC) 2 banks
#define AT91C_SDRAMC_NB_4_BANKS ((unsigned int) 0x1 << 4) // (SDRAMC) 4 banks
#define AT91C_SDRAMC_CAS ((unsigned int) 0x3 << 5) // (SDRAMC) CAS Latency
#define AT91C_SDRAMC_CAS_2 ((unsigned int) 0x2 << 5) // (SDRAMC) 2 cycles
#define AT91C_SDRAMC_CAS_3 ((unsigned int) 0x3 << 5) // (SDRAMC) 3 cycles
#define AT91C_SDRAMC_DBW ((unsigned int) 0x1 << 7) // (SDRAMC) Data Bus Width
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