📄 f350_adc_buffered_2.lst
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*** WARNING C280 IN LINE 59 OF F350_ADC_BUFFERED_2.C: 'e33': unreferenced local variable
*** WARNING C280 IN LINE 59 OF F350_ADC_BUFFERED_2.C: 'e44': unreferenced local variable
*** WARNING C280 IN LINE 60 OF F350_ADC_BUFFERED_2.C: 'e1': unreferenced local variable
*** WARNING C280 IN LINE 60 OF F350_ADC_BUFFERED_2.C: 'e2': unreferenced local variable
*** WARNING C280 IN LINE 60 OF F350_ADC_BUFFERED_2.C: 'e3': unreferenced local variable
*** WARNING C280 IN LINE 60 OF F350_ADC_BUFFERED_2.C: 'e4': unreferenced local variable
169
170
C51 COMPILER V7.50 F350_ADC_BUFFERED_2 08/12/2007 15:58:07 PAGE 4
171 //-----------------------------------------------------------------------------
172 // SYSCLK_Init
173 //-----------------------------------------------------------------------------
174 //
175 // This routine initializes the system clock to use the internal 24.5MHz
176 // oscillator as its clock source, with x 2 multiply for
177 // 49 MHz operation. Also enables missing clock detector reset.
178 //
179 void SYSCLK_Init (void)
180 {
181 1 unsigned i;
182 1
183 1 OSCICN = 0x80; // enable intosc
184 1 CLKSEL = 0x00; // select intosc as sysclk source
185 1
186 1 // INTOSC configure
187 1
188 1 OSCICN = 0x83;
189 1
190 1 // PLL configure
191 1
192 1 CLKMUL = 0x00; // Reset Clock Multiplier
193 1
194 1 CLKMUL &= ~0x03; // select INTOSC / 2 as PLL source
195 1
196 1 CLKMUL |= 0x80; // Enable 4x Multipler (MULEN = 1)
197 1
198 1 for (i = 0; i < 125; i++); // Delay for at least 5us
199 1
200 1 CLKMUL |= 0xC0; // Initialize Multiplier
201 1
202 1 while (!(CLKMUL & 0x20)); // Poll for Multiply Ready
203 1
204 1 // SYSCLK configure
205 1
206 1 VDM0CN = 0x80; // enable VDD monitor
207 1 RSTSRC = 0x06; // enable missing clock detector
208 1 // and VDD monitor reset sources
209 1 CLKSEL = 0x02; // select PLL as clock source
210 1 }
211
212 //-----------------------------------------------------------------------------
213 // PORT_Init
214 //-----------------------------------------------------------------------------
215 //
216 // Configure the Crossbar and GPIO ports.
217 // P0.4 - TX0 (push-pull)
218 // P0.5 - RX0
219
220 void PORT7_Init (void)
221 {
222 1 XBR0 |= 0x01; // UART0 Selected
223 1 XBR1 |= 0x40; // Enable crossbar and weak pull-ups
224 1 P0MDOUT |= 0xD0; // TX, LEDs = Push-pull
225 1 }
226
227 //-----------------------------------------------------------------------------
228 // ADC0_Init extVREF Bipolar AIN0.1-AIN0.0
229 //-----------------------------------------------------------------------------
230 //
231 // This function initializes the ADC to measure across AIN0.1 and AIN0.0
232 // on the Target Board (Differential measurements, Bipolar codes)
C51 COMPILER V7.50 F350_ADC_BUFFERED_2 08/12/2007 15:58:07 PAGE 5
233
234 void ADC0_Init (void)
235 {
236 1 unsigned ADC0_decimation;
237 1
238 1 REF0CN &= ~0x01; // disable internal vref
239 1
240 1 // REF0CN |= 0x01; // (enable if using internal vref)
241 1
242 1
243 1 // ADC0CN = 0x00; // unipolar output codes, GAIN=1
244 1 ADC0CN = 0x10; // Bipolar output codes, GAIN=1
245 1
246 1 // ADC0CF = 0x00; // interrupts upon SINC3 filter output
247 1 // and uses internal VREF
248 1
249 1 ADC0CF = 0x04; // interrupts upon SINC3 filter output
250 1 // and uses external VREF
251 1
252 1
253 1 ADC0CLK = (SYSCLK/MDCLK)-1; // Ideally, MDCLK = 2.4576 MHz
254 1
255 1 // Generate MDCLK for modulator.
256 1
257 1
258 1
259 1 // program decimation rate for desired OWR
260 1
261 1 ADC0_decimation = (unsigned long) SYSCLK/ (unsigned long) OWR /
262 1 (unsigned long) (ADC0CLK+1)/(unsigned long)128;
263 1
264 1 ADC0_decimation--;
265 1
266 1 ADC0DEC = ADC0_decimation;
267 1
268 1
269 1 ADC0BUF = 0x00; // 关闭输入缓冲
270 1
271 1
272 1 ADC0MUX = 0x01; // 差分输入
273 1 // AIN+ => AIN0.0
274 1 // AIN- => AIN0.1
275 1
276 1
277 1
278 1
279 1
280 1 ADC0MD |= 0x80; // 使能(IDLE Mode)
281 1 }
282
283 //-----------------------------------------------------------------------------
284 // UART0_Init
285 //-----------------------------------------------------------------------------
286 //
287 // Configure the UART0 using Timer1, for <BAUDRATE> and 8-N-1.
288 //
289 void UART0_Init (void)
290 {
291 1 SCON0 = 0x10; // 8-bit variable bit rate
292 1 // level of STOP bit is ignored
293 1 // RX enabled
294 1 // ninth bits are zeros
C51 COMPILER V7.50 F350_ADC_BUFFERED_2 08/12/2007 15:58:07 PAGE 6
295 1 // clear RI0 and TI0 bits
296 1 if (SYSCLK/BAUDRATE/2/256 < 1)
297 1 {
298 2 TH1 = -(SYSCLK/BAUDRATE/2);
299 2 CKCON |= 0x08; // T1M = 1; SCA1:0 = xx
300 2 }
301 1 else if (SYSCLK/BAUDRATE/2/256 < 4)
302 1 {
303 2 TH1 = -(SYSCLK/BAUDRATE/2/4);
304 2 CKCON &= ~0x0B; // T1M = 0; SCA1:0 = 01
305 2 CKCON |= 0x01;
306 2 }
307 1 else if (SYSCLK/BAUDRATE/2/256 < 12)
308 1 {
309 2 TH1 = -(SYSCLK/BAUDRATE/2/12);
310 2 CKCON &= ~0x0B; // T1M = 0; SCA1:0 = 00
311 2 }
312 1 else
313 1 {
314 2 TH1 = -(SYSCLK/BAUDRATE/2/48);
315 2 CKCON &= ~0x0B; // T1M = 0; SCA1:0 = 10
316 2 CKCON |= 0x02;
317 2 }
318 1
319 1 TL1 = TH1; // init Timer1
320 1 TMOD &= ~0xf0; // TMOD: timer 1 in 8-bit autoreload
321 1 TMOD |= 0x20;
322 1 TR1 = 1; // START Timer1
323 1 TI0 = 1; // Indicate TX0 ready
324 1 }
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 664 ----
CONSTANT SIZE = 96 ----
XDATA SIZE = 512 ----
PDATA SIZE = ---- ----
DATA SIZE = 6 40
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 9 WARNING(S), 0 ERROR(S)
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