class.ptf

altera的ip核

CLASS user_logic_Open_I2C
{
   ASSOCIATED_FILES 
   {
      Add_Program = "";
      Edit_Program = "";
      Generator_Program = "mk_user_logic_Open_I2C.pl";
   }
   MODULE_DEFAULTS 
   {
      class = "user_logic_Open_I2C";
      class_version = "2.0";
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Date_Modified = "--unknown--";
         Clock_Source = "clk";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
      }
      SLAVE avalonS
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Address_Alignment = "native";
            Address_Width = "3";
            Data_Width = "8";
            Has_IRQ = "1";
            Has_Base_Address = "1";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Setup_Time = "0";
            Hold_Time = "0";
            Is_Memory_Device = "0";
            Uses_Tri_State_Data_Bus = "0";
            Is_Enabled = "1";
         }
         PORT_WIRING 
         {
            PORT wb_clk_i
            {
               width = "1";
               direction = "input";
               type = "clk";
            }
            PORT wb_rst_i
            {
               width = "1";
               direction = "input";
               type = "always0";
            }
            PORT arst_i
            {
               width = "1";
               direction = "input";
               type = "reset_n";
            }
            PORT wb_adr_i
            {
               width = "3";
               direction = "input";
               type = "address";
            }
            PORT wb_dat_i
            {
               width = "8";
               direction = "input";
               type = "writedata";
            }
            PORT wb_dat_o
            {
               width = "8";
               direction = "output";
               type = "readdata";
            }
            PORT wb_we_i
            {
               width = "1";
               direction = "input";
               type = "write";
            }
            PORT wb_stb_i
            {
               width = "1";
               direction = "input";
               type = "chipselect";
            }
            PORT wb_cyc_i
            {
               width = "1";
               direction = "input";
               type = "chipselect";
            }
            PORT wb_ack_o
            {
               width = "1";
               direction = "output";
               type = "waitrequest_n";
            }
            PORT wb_inta_o
            {
               width = "1";
               direction = "output";
               type = "irq";
            }
            PORT scl_pad_i
            {
               width = "1";
               direction = "input";
               type = "export";
            }
            PORT scl_pad_o
            {
               width = "1";
               direction = "output";
               type = "export";
            }
            PORT scl_padoen_o
            {
               width = "1";
               direction = "output";
               type = "export";
            }
            PORT sda_pad_i
            {
               width = "1";
               direction = "input";
               type = "export";
            }
            PORT sda_pad_o
            {
               width = "1";
               direction = "output";
               type = "export";
            }
            PORT sda_padoen_o
            {
               width = "1";
               direction = "output";
               type = "export";
            }
         }
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL a
            {
               name = "wb_clk_i";
            }
            SIGNAL b
            {
               name = "wb_rst_i";
            }
            SIGNAL c
            {
               name = "arst_i";
            }
            SIGNAL d
            {
               name = "wb_adr_i";
               radix = "hexadecimal";
            }
            SIGNAL e
            {
               name = "wb_dat_i";
               radix = "hexadecimal";
            }
            SIGNAL f
            {
               name = "wb_dat_o";
               radix = "hexadecimal";
            }
            SIGNAL g
            {
               name = "wb_we_i";
            }
            SIGNAL h
            {
               name = "wb_stb_i";
            }
            SIGNAL i
            {
               name = "wb_cyc_i";
            }
            SIGNAL j
            {
               name = "wb_ack_o";
            }
            SIGNAL k
            {
               name = "wb_inta_o";
            }
            SIGNAL l
            {
               name = "scl_pad_i";
            }
            SIGNAL m
            {
               name = "scl_pad_o";
            }
            SIGNAL n
            {
               name = "scl_padoen_o";
            }
            SIGNAL o
            {
               name = "sda_pad_i";
            }
            SIGNAL p
            {
               name = "sda_pad_o";
            }
            SIGNAL q
            {
               name = "sda_padoen_o";
            }
         }
      }
   }
   USER_INTERFACE 
   {
      USER_LABELS 
      {
         name = "Open_I2C";
         technology = "User Logic";
      }
   }
   DEFAULT_GENERATOR 
   {
      top_module_name = "i2c_master_top";
      black_box = "0";
      vhdl_synthesis_files = "";
      verilog_synthesis_files = "i2c_master_bit_ctrl.v,i2c_master_byte_ctrl.v,i2c_master_defines.v,i2c_master_top.v";
      black_box_files = "";
   }
}