vga_controller.pm

altera的ip核

use strict;
use europa_all;

my $slave_name = 's1';
my $master_name = 'm1';

my $VGA_DAC_LATENCY = 8;

#####################################################################################
#                    SIGNAL TIMING FOR 640 x 480 VGA 60Hz                           #
#####################################################################################

my %vga_640x480_60Hz_timing;

$vga_640x480_60Hz_timing{"HSCAN_WIDTH"} = 800;
$vga_640x480_60Hz_timing{"VSCAN_DEPTH"} = 524;
$vga_640x480_60Hz_timing{"NUM_COLUMNS"} = 640;
$vga_640x480_60Hz_timing{"NUM_ROWS"} = 480;   

########################## HORIZONTAL TIMING CONSTANTS ###############################
# hblank                                   --------  ...  -----------
#       ___________________________________|                        |_________
# hsync ----------               ------------------  ...  -----------------
#                 |______________|                                        |____
# count           0              94       140                      781  794,0
#            HSYNC_LOW1     HSYNC_HIGH  HBLANK_HIGH         HBLANK_LOW  $HSYNC_LOW2
#
######################################################################################
$vga_640x480_60Hz_timing{"HSYNC_LOW1"} = 0;   
$vga_640x480_60Hz_timing{"HSYNC_LOW2"} = 800; 
$vga_640x480_60Hz_timing{"HSYNC_HIGH"} = 96;  
$vga_640x480_60Hz_timing{"HBLANK_HIGH"} = 144;
$vga_640x480_60Hz_timing{"HBLANK_LOW"} = 784; 

############################ VERTICAL TIMING CONSTANTS ###############################
# vblank -------                           --------  ...  -----------
#              |___________________________|                        |_________
# vsync ----------      ---------------------------  ...  ------------------
#                 |_____|                                                   |____
# linecount       0     2                 34                      514      528,0
#          VSYNC_LOW1 VSYNC_HIGH      VBLANK_HIGH             VBLANK_LOW  $VSYNC_LOW2
#
######################################################################################
$vga_640x480_60Hz_timing{"VSYNC_LOW1"} = 0;  
$vga_640x480_60Hz_timing{"VSYNC_LOW2"} = 524;
$vga_640x480_60Hz_timing{"VSYNC_HIGH"} = 2;  
$vga_640x480_60Hz_timing{"VBLANK_HIGH"} = 33;
$vga_640x480_60Hz_timing{"VBLANK_LOW"} = 513;
$vga_640x480_60Hz_timing{"SYNC_POLARITY"} = 0;  

######################################################################################

#####################################################################################
#                    SIGNAL TIMING FOR 800 x 600 VGA 60Hz                           #
#####################################################################################

my %vga_800x600_60Hz_timing;

$vga_800x600_60Hz_timing{"HSCAN_WIDTH"} = 1056;
$vga_800x600_60Hz_timing{"VSCAN_DEPTH"} = 628; 
$vga_800x600_60Hz_timing{"NUM_COLUMNS"} = 800; 
$vga_800x600_60Hz_timing{"NUM_ROWS"} = 600;    
$vga_800x600_60Hz_timing{"HSYNC_LOW1"} = 0;    
$vga_800x600_60Hz_timing{"HSYNC_LOW2"} = 1056; 
$vga_800x600_60Hz_timing{"HSYNC_HIGH"} = 128;  
$vga_800x600_60Hz_timing{"HBLANK_HIGH"} = 181; 
$vga_800x600_60Hz_timing{"HBLANK_LOW"} = 981;  
$vga_800x600_60Hz_timing{"VSYNC_LOW1"} = 0;    
$vga_800x600_60Hz_timing{"VSYNC_LOW2"} = 628;  
$vga_800x600_60Hz_timing{"VSYNC_HIGH"} = 4;    
$vga_800x600_60Hz_timing{"VBLANK_HIGH"} = 17;  
$vga_800x600_60Hz_timing{"VBLANK_LOW"} = 617;  
$vga_800x600_60Hz_timing{"SYNC_POLARITY"} = 1;  

######################################################################################

#####################################################################################
#                    SIGNAL TIMING FOR 1024 x 768 VGA 60Hz                          #
#####################################################################################

my %vga_1024x768_60Hz_timing;

$vga_1024x768_60Hz_timing{"HSCAN_WIDTH"} = 1344;
$vga_1024x768_60Hz_timing{"VSCAN_DEPTH"} = 806;
$vga_1024x768_60Hz_timing{"NUM_COLUMNS"} = 1024;
$vga_1024x768_60Hz_timing{"NUM_ROWS"} = 768;
$vga_1024x768_60Hz_timing{"HSYNC_LOW1"} = 0;
$vga_1024x768_60Hz_timing{"HSYNC_LOW2"} = 1344;
$vga_1024x768_60Hz_timing{"HSYNC_HIGH"} = 136;
$vga_1024x768_60Hz_timing{"HBLANK_HIGH"} = 296;
$vga_1024x768_60Hz_timing{"HBLANK_LOW"} = 1320;
$vga_1024x768_60Hz_timing{"VSYNC_LOW1"} = 0;
$vga_1024x768_60Hz_timing{"VSYNC_LOW2"} = 806;
$vga_1024x768_60Hz_timing{"VSYNC_HIGH"} = 6;
$vga_1024x768_60Hz_timing{"VBLANK_HIGH"} = 35;
$vga_1024x768_60Hz_timing{"VBLANK_LOW"} = 803;
$vga_1024x768_60Hz_timing{"SYNC_POLARITY"} = 0;  

	
######################################################################################

sub vga_controller
{
  # Simple syntax check is invoked with no parameters.
  return if !@_;

  my $project = e_project->new(@_);

  make($project);
  $project->output();
}

sub make_slave_interface(@)
{
  my %type_map;

  $type_map{"slave_address"} = "address";
  $type_map{"slave_write"} = "write";
  $type_map{"slave_writedata"} = "writedata";
  $type_map{"slave_readdata"} = "readdata";
  $type_map{"slave_chipselect"} = "chipselect";
  $type_map{"clk"} = "clk";
  $type_map{"reset_n"} = "reset_n";

  e_avalon_slave->add({
    name => $slave_name,
    type_map => \%type_map,
  });
}

sub make_master_interface(@)
{
  my %type_map;

  $type_map{"master_address"} = "address";
  $type_map{"master_readdata"} = "readdata";
  $type_map{"master_read"} = "read";
  $type_map{"master_waitrequest"} = "waitrequest";
  $type_map{"master_data_valid"} = "readdatavalid";
  $type_map{"clk"} = "clk";

  e_avalon_master->add({
    name => $master_name,
    type_map => \%type_map,
  });
}

sub make($)
{
  my $project = shift;

  my $module = $project->top();
  my $marker = e_default_module_marker->new($module);

  my $mod_ptf = $project->system_ptf()->{"MODULE " . $module->name()};

  # Work with genuine writeable-to-ptf WSA and SBI hashes.
  my $SBI_slave = $mod_ptf->{"SLAVE $slave_name"}->{SYSTEM_BUILDER_INFO};
  my $SBI_master = $mod_ptf->{"MASTER $master_name"}->{SYSTEM_BUILDER_INFO};
  my $WSA = $mod_ptf->{WIZARD_SCRIPT_ARGUMENTS};

  ######################### VGA TIMING CONSTANTS #####################

	my $width = $WSA->{screen_width};
	my $height = $WSA->{screen_height};
#	print STDERR "Width = $width, Height = $height\n";

	# Here we choose which timing values we're going to use based on the wizard settings.
	my %vga_timing;
	my $key;
	my $value;

	if ($WSA->{screen_resolution} eq "640x480")
	{
		while (($key, $value) = each(%vga_640x480_60Hz_timing))
		{
			$vga_timing{$key} = $vga_640x480_60Hz_timing{$key};
		}
#	  e_signal->add({name => "clk_25", width => 1,});
#		e_assign->add (["vga_clk", "clk_25"]);
		
		print STDERR "VGA Controller resolution has been set to 640x480\n";
		print STDERR "Ensure that vga_clk is connected to a 25MHz clock\n";
	}
	if ($WSA->{screen_resolution} eq "800x600")
	{
		while (($key, $value) = each(%vga_800x600_60Hz_timing))
		{
			$vga_timing{$key} = $vga_800x600_60Hz_timing{$key};
		}
#	  e_signal->add({name => "clk_40", width => 1,});
#		e_assign->add (["vga_clk", "clk_40"]);
		
		print STDERR "VGA Controller resolution has been set to 800x600\n";
		print STDERR "Ensure that vga_clk is connected to a 40MHz clock\n";
	}
	if ($WSA->{screen_resolution} eq "1024x768")
	{
		while (($key, $value) = each(%vga_1024x768_60Hz_timing))
		{
			$vga_timing{$key} = $vga_1024x768_60Hz_timing{$key};
		}
#	  e_signal->add({name => "clk_65", width => 1,});
#		e_assign->add (["vga_clk", "clk_65"]);
		
		print STDERR "VGA Controller resolution has been set to 1024x768\n";
		print STDERR "Ensure that vga_clk is connected to a 65MHz clock\n";
	}

  my $HSCAN_WIDTH = $vga_timing{'HSCAN_WIDTH'};
  my $VSCAN_DEPTH = $vga_timing{'VSCAN_DEPTH'};
  my $NUM_COLUMNS = $vga_timing{'NUM_COLUMNS'};
  my $NUM_ROWS = $vga_timing{'NUM_ROWS'};
  my $HSYNC_LOW1 = $vga_timing{'HSYNC_LOW1'};
  my $HSYNC_LOW2 = $vga_timing{'HSYNC_LOW2'};
  my $HSYNC_HIGH = $vga_timing{'HSYNC_HIGH'};
  my $HBLANK_HIGH = $vga_timing{'HBLANK_HIGH'};
  my $HBLANK_LOW = $vga_timing{'HBLANK_LOW'};
  my $VSYNC_LOW1 = $vga_timing{'VSYNC_LOW1'};
  my $VSYNC_LOW2 = $vga_timing{'VSYNC_LOW2'};
  my $VSYNC_HIGH = $vga_timing{'VSYNC_HIGH'};
  my $VBLANK_HIGH = $vga_timing{'VBLANK_HIGH'};
  my $VBLANK_LOW = $vga_timing{'VBLANK_LOW'};
  my $SYNC_POLARITY = $vga_timing{'SYNC_POLARITY'};

  ################################################################
  #                     THIS IS THE DMA FIFO                     #
  ################################################################

  ####################### FIFO CONSTANTS #########################

  my $FIFO_DEPTH = $WSA->{fifo_depth};
  my $FIFO_WRITE_THRESHOLD = ($WSA->{fifo_depth} * 7 / 8);
  my $FIFO_READ_THRESHOLD = ($WSA->{fifo_depth} / 2);

  # These ports are for debugging only.
  #e_port->add({name => "fifo_data_out", width => $SBI_master->{Data_Width}, direction => "output", });
  #e_port->add({name => "fifo_used", width => 12, direction => "output", });

  # We need to declare the width of these signals
  my $fifo_counter_width = ceil(log2($FIFO_DEPTH));
  e_signal->add({name => "fifo_data_out", width => 32,});
  e_signal->add({name => "fifo_data_in", width => 32,});
  e_signal->add({name => "fifo_used", width => "$fifo_counter_width",});

  e_blind_instance->add({
     tag            => 'normal',
     use_sim_models => 1,
     name           => 'the_dcfifo',
     module         => 'dcfifo',
     in_port_map    => {data => "fifo_data_in",
                        rdclk => "vga_clk",
                        rdreq => "fifo_read_req",
                        wrclk => "fifo_write_clk",
                        wrreq => "fifo_write_req",
                        aclr => "!reset_n",},
     out_port_map   => {"q", "fifo_data_out",
                        wrusedw => "fifo_used",
                        rdempty => "fifo_rdempty",},
#                         wrfull => "fifo_wrfull"},
     parameter_map  => {LPM_WIDTH => "32",
                      LPM_NUMWORDS => $FIFO_DEPTH,
                      LPM_SHOWAHEAD => "\"ON\""},
  });

  e_assign->add (["fifo_write_clk", "clk"]);
  e_assign->add (["fifo_data_in", "master_readdata"]);

  # This is our signal that the fifo has fallen below the write threshold, and
  # should be written with some data as soon as possible.  We double register
  # it to avoid any possible clock-crossing metastability issues.
  e_register->add({
    out => {name => "fifo_has_room_reg1", export => 0,},
    in => "fifo_used < $FIFO_WRITE_THRESHOLD",
    enable => 1,
  });
  e_register->add({
    out => {name => "fifo_has_room", export => 0,},
    in => "fifo_has_room_reg1",
    enable => 1,
  });

  # This is our signal that the fifo has reached the read threshold
  # and we can start reading out of it.  We double register it to
  # avoid any possible clock-crossing metastability issues.
  e_register->add({
    out => {name => "fifo_has_data_reg1", export => 0,},
    in => "fifo_used > $FIFO_READ_THRESHOLD",
    clock => "vga_clk",
    enable => 1,