📄 init.s
字号:
; Step 3
; Set SDRAM Initialization to PALL in Dynamic Control Register
; This issues a Precharge all instruction to SDRAM
; --------------------------------------------------------------------------------
LDR r1, =MPMC_Dyn_Ctl ; Address of PMC SDRAM Control Register
LDR r2, =0x00000103 ; Issue PALL command (Pre-charge all)
STR r2, [r1]
; Step 4
; Perform a number of refreshes by writing 2 into the Refresh Register
; --------------------------------------------------------------------------------
LDR r1, =MPMC_Dyn_Refr ; Address of PMC SDRAM Refresh Register
LDR r2, =0x2 ; Perform a refresh every 32 clock cycles
STR r2, [r1]
; Step 5
; Wait until two SDRAM refresh cycles have occurred (Total of 64 clock cycles)
; --------------------------------------------------------------------------------
LDR r1, =0x20
6 SUB r1, r1, #1
CMP r1,#0
BNE %B6
; Step 6
; Program required operational value into refresh register
;
; ( (15.625 uS refresh time) * ( 16 mhz low power clk to PMC) )/16 = 16 or 0x10 or
; ( (15.625 uS refresh time) * ( 10 mhz HAPS clk to PMC) )/16 = 9 or 0x09 or
; ( (15.625 uS refresh time) * ( 66 mhz High power clk to PMC) )/16 = 65 or 0x41
; --------------------------------------------------------------------------------
LDR r1, =MPMC_Dyn_Refr ; Address of PMC SDRAM Refresh Register
LDR r2, =0x10 ; Set for Perform a refresh every 790 clock cycles
STR r2, [r1] ; to meet 15.625 usec refresh requirement
; Step 7
; Program RAS & CAS Latency values
; --------------------------------------------------------------------------------
LDR r1, =MPMC_Dyn_RC0 ; Address of PMC RAS/CAS CS0 Register
LDR r2, =0x202 ; Micron Spec (<=100MHz RAS/CAS Latency=2)
STR r2, [r1]
; Step 8
; Program the operational values into the configuration register.
; --------------------------------------------------------------------------------
LDR r1, =MPMC_Dyn_Cfg0 ; Address of PMC CS0 Configuration Register
LDR r2, =0x280 ; see above for bit breakdown
STR r2, [r1]
; Step 9
; Set the SDRAM Initialization value to MODE in the Dynamic Control Register
; --------------------------------------------------------------------------------
LDR r1, =MPMC_Dyn_Ctl ; Issue SDRAM Mode command
LDR r2, =0x83
STR r2, [r1]
; Step 10
; Program the SDRAM Mode
;
; The Micron SDRAM Mode value is applied to the SDRAM by reading
; from the SDRAM rather than writing a value to it. The read
; address contains the data field of the desired mode to be applied.
; Below is an example of how the read address is derived.
;
; See Micron MT48LCM16A2 spec for example bit assignments:
;
; Burst length = PMC does quad 32-bit word burst, for a 16 bit bus, value of 8 (011)
; Burst type = sequential (0)
; Cas latency = 2 for a -7E part (<=133MHz) (010)
; Operating mode = standard operation (0)
; Write burst mode = programmed burst length (0)
; Reserved = (00)
;
; The bit values above create a combined value of 0x023hex. This
; value is applied via address lines a11-a0 on the SDRAM. To get
; the bit values on the proper address lines out of the PMC and
; onto the SDRAM device, they must be shifted per the 16bit data
; bus table for 64M SDRAM (4MX16,RBC) on page 6-36 of the ARM PrimeCell
; MultiPort Memory Controller (PL172) Specification.
; A value of 0x23hex value has bits A5,A1 & A0 set to logic one at the SDRAM.
; The table on page 6-36 requires that AHB address to row address bits
; A16,A12, A11 must be set to logic one to get the 0x23hex value out to the SDRAM.
; In addition to the bit shifting, the eight most significant bits of the
; read address must be set to 0xFC which activates the SDRAM Chip Select(CS3)
; per the DDP2000 memory map.
;
; The combined mode value bit shifting and required SDRAM selection address
; results in an address value of 0xFC011800.
;
; In conclusion, programming the SDRAM mode with a value of 0x23hex requires
; a read from address 0xFC011800.
;
; --------------------------------------------------------------------------------
LDR r1, =SDRAM_MODE ; Issue SDRAM Mode command
LDR r2, [r1] ; Read from SDRAM to set the SDRAM Mode
; Before re-enabling the SDRAM setup the rest of the PMC SDRAM registers for
; optimized operation
; Complete the SDRAM initialization process by issuing the Normal command and
; enabling the SDRAM buffers
; Step 11
; Set the SDRAM Initialization value to Normal in the Dynamic Control Register
; --------------------------------------------------------------------------------
LDR r1, =MPMC_Dyn_Ctl ; Issue SDRAM Normal command
LDR r2, =0x00000002 ;
STR r2, [r1]
; Step 12
; Enable the buffers in the Dynamic configuration register.
; --------------------------------------------------------------------------------
LDR r1, =MPMC_Dyn_Cfg0 ; Address of PMC Dynamic CS0 Configuration Register
LDR r2, [r1] ; Get current configuration
ORR r3, r2, #BIT19 ; Enable buffers
STR r3, [r1]
SKIP_SDRAM_INIT
ENDIF ; END OF CONDITIONAL COMPILE OF SDRAM DEFINE
;******************************************************************************
;* Intialization of Static Memory Device - IDT71V016SA
;*
;* Attached to Chip Select 2(CS2), mapped to starting address 0xFB000000
;*
;* Note that this initialization is also required if CS2 is used to address
;* memory-mapped IO devices.
;*
;* The DDP2230 provides four, 4-word write buffers in the ARM processor's
;* memory controller. These buffers provide cache-like functionality for
;* ARM memory accesses. When CS2 is used to access peripheral devices, the
;* buffering must be disabled to ensure that memory reads are made from the
;* peripheral rather than from a buffer.
;******************************************************************************
; If CS2 decoding requires the use of A23, include the following three instructions
; to enable A23 on GPIO34
; --------------------------------------------------------------------------------
; --------------------------------------------------------------------------------
; LDR r1,=GPIO_32_47_ENABLE ; Ensure that A23 is enabled
; LDR r2,=0xfffffff8
; STR r2,[r1]
; If CS2 is used for peripheral device addressing, include the following instruction
; --------------------------------------------------------------------------------
; LDR r2, =0x00000081 ; Disable write buffering
; If CS2 is used for peripheral device addressing, exclude the following instruction
; --------------------------------------------------------------------------------
LDR r2, =0x00080081 ; Enable write buffering
; Define state of write buffer enable; Also set memory width to 16 bits
; --------------------------------------------------------------------------------
LDR r1, =MPMC_STA_CFG2 ; Static memory configuration Register 2
STR r2, [r1]
; Continue
; --------------------------------------------------------------------------------
; --------------------------------------------------------------------------------
; --------------------------------------------------------------------------------
LDR r1, =MPMC_STA_WT_R2 ; Static Memory Read Delay Register
LDR r2, =0x0000001 ; Nonpage mode read or asynchronous
STR r2, [r1] ; page mode read WaitRD = 1
LDR r1, =MPMC_STA_WT_W2 ; Static Memory Write Delay Registers
LDR r2, =0x0000000 ; SRAM wait state time for write accesses
STR r2, [r1] ; after the first read = 0
LDR r1, =MPMC_STA_WT_T2 ; Static Memory Turn Round Delay Registers
LDR r2, =0x0000000 ; Bus turnaround cycles = 1
STR r2, [r1] ;
;******************************************************************************
; C DATA INITIALIZATION BY SCATTER LOAD METHOD
;
; This section of source moves the realtime code from flash to ITCM,
; moves initialized data to DTCM and sets up ZI.
;******************************************************************************
IMPORT |Load$$RWDATA$$Base| ; Load View addr of RWDATA Region in scatter file
IMPORT |Image$$RWDATA$$Base| ; Execution View addr RWDATA Region
IMPORT |Image$$RWDATA$$ZI$$Base| ; End of RW/Start of ZI area in RWDATA Region
IMPORT |Image$$RWDATA$$ZI$$Limit| ; End of ZI area in RWDATA Region
LDR r0,=|Load$$RWDATA$$Base| ; Get copy src addr to RW data area
LDR r1,=|Image$$RWDATA$$Base| ; Get copy dest addr for RW data area
LDR r3,=|Image$$RWDATA$$ZI$$Base| ; Get addr for end of RW area/Start of ZI area
0 CMP r1,r3 ; Test dest addr = addr for End of RW data area
LDRCC r2,[r0],#4 ; Move RW data to temp reg, post incr by 4 bytes
STRCC r2,[r1],#4 ; Move RW data to dest, post incr by 4 bytes
BCC %B0 ; Loop until dest addr = end of RW data area
1 LDR r1,=|Image$$RWDATA$$ZI$$Limit| ; End of ZI area, r3 contains start of ZI area
MOV r2,#0 ; Load 0x0 into reg for init of ZI
2 CMP r3,r1 ; Test ZI dest addr = end of ZI data area
STRCC r2,[r3],#4 ; Store 0x0 in ZI data area, post incr addr 4 bytes
BCC %B2 ; Loop until dest addr = end of ZI data area
;
; Move performance critical code to internal I-TCM @0x00000080 (scatter.txt)
;
IMPORT |Load$$ITCM$$Base| ; Load View addr of ITCM region in scatter file
IMPORT |Image$$ITCM$$Base| ; Execution View addr of ITCM Region in scatter file
IMPORT |Image$$ITCM$$Limit| ; End of ITCM code region
LDR r0, =|Load$$ITCM$$Base| ; Get copy src addr of Load View ITCM code region
LDR r1, =|Image$$ITCM$$Base| ; Get copy dest addr for Execution View ITCM code region
LDR r2, =|Image$$ITCM$$Limit| ; Get addr for end of Execution View ITCM code region
3 cmp r1,r2 ; Test dest addr = End of ITCM Region
LDRCC r3,[r0],#4 ; Move ITCM code to temp reg, post incr by 4 bytes
STRCC r3,[r1],#4 ; Move ITCM code to ITCM dest addr, post incr by 4 bytes
BCC %B3 ; Loop until dest addr = end of ITCM code area
;
; Move remainder of read-only code and constant data to SDRAM if the target
; is to execute with no ROM accesses.
;
IF :DEF:DEFINE_RO_SDRAM
IMPORT |Load$$ROCODE$$Base| ; Load View addr of ROCODE region in scatter file
IMPORT |Image$$ROCODE$$Base| ; Execution View addr of ROCODE Region in scatter file
IMPORT |Image$$ROCODE$$Limit| ; End of ROCODE code region
LDR r0, =|Load$$ROCODE$$Base| ; Get copy src addr of Load View ROCODE code region
LDR r1, =|Image$$ROCODE$$Base| ; Get copy dest addr for Execution View ROCODE code region
LDR r2, =|Image$$ROCODE$$Limit| ; Get addr for end of Execution View ROCODE code region
4 CMP r1,r2 ; Test dest addr = End of ROCODE Region
LDRCC r3,[r0],#4 ; Move ROCODE code to temp reg, post incr by 4 bytes
STRCC r3,[r1],#4 ; Move ROCODE code to ROCODE dest addr, post incr by 4 bytes
BCC %B4 ; Loop until dest addr = end of ROCODE code area
ENDIF
;
; Color the system stack area for later use in determining stack usage
;
LDR r1,=HEAP_End
LDR r3,=Stack_Limit
LDR r2,=0x64657266
7 CMP r1,r3
STRCC r2,[r1],#4
BCC %B7
;
; IRQ stack pointer register initialization
; Enter IRQ mode and set up the IRQ stack pointer
;
MOV r0, #Mode_IRQ:OR:I_Bit:OR:F_Bit ; Interrupts disabled
MSR CPSR_c, r0 ; Enter IRQ mode
LDR r1, =IRQ_Stack ; Get IRQ stack pointer
BIC r1, r1, #7 ; Ensure 8-byte alignment
MOV sp, r1 ; Save stack ptr in a banked
; private copy of R13 for
; IRQ mode use only
MOV r0, #Mode_SVC:OR:I_Bit:OR:F_Bit ; Interrupts disabled
MSR CPSR_c, r0 ; Enter SVC mode
LDR r3, SYS_STACK_PTR ; Pickup stack pointer
STR r1, [r3, #0] ; Save the system stack
LDR r1, =SVC_Stack ; Get SVC stack pointer
BIC r1, r1, #7 ; Ensure 8-byte alignment
MOV sp, r1 ; Save stack ptr in a banked
; private copy of R13 for
; IRQ mode use only
;
; Enter the C code
;
IMPORT C_Entry
;
; Branch to application entry point
;
IF :DEF:THUMB
ORR lr, pc, #1
BX lr
CODE16 ; Next instruction will be Thumb
ENDIF
LDR r12,=C_Entry ; save this in register for possible long jump
BX r12 ; branch to __main
;
; Should never return from C_Entry during normal Execution
;
ENDLESS_LOOP
B ENDLESS_LOOP
SYS_STACK_PTR
DCD _tx_thread_system_stack_ptr
UNUSED_MEMORY
DCD _tx_initialize_unused_memory
END ; End of file marker.
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -