init.s

IT projecotr reference design.

POWERUP_WAIT    EQU     0x400

ARM_PBC_RSVD    EQU     0x11009000       ; Reserved register used to track   
                                         ; SDRAM initialization status
SDRAM_INIT_MASK EQU     0x00000002       ; SDRAM Init Status bit mask
 
GPIO_32_47_ENABLE EQU   0x1100f02c       ;
    
HW_CFG_REG      EQU     0x1100eff0       ; Hardware configuration register
     
PMC_CSZ_0       EQU     0x11020000       ; PMC CSZ0 configuration register



;---Exception Vector Table Definition
                                       
    AREA    Init, CODE, READONLY
    
    IMPORT handler_undefined_instr
    IMPORT handler_SWI
    IMPORT handler_prefetch_abort
    IMPORT handler_data_abort 
    IMPORT handler_irq
    IMPORT handler_fiq
    
    IMPORT      _tx_thread_system_stack_ptr
    IMPORT      _tx_initialize_unused_memory

    CODE32

    EXPORT  __main  ; defined to ensure that C runtime system
                    ; is not linked in

    ALIGN          
    ENTRY
    CODE32

;--- Define entry point
__main


; The RESET entry point
Reset_Handler


;---Move Exception Table to ITCM @ address 0x00000000

    LDR r0,=INT_Vectors
    MOV r1,#0
    LDMIA   r0!,{r2-r9}
    STMIA   r1!,{r2-r9}         ; 32 bytes moved
    LDMIA   r0!,{r2-r9}
    STMIA   r1!,{r2-r9}         ; 64 bytes moved
    
    B       SkipTable

;  WARNING: Don't move INT_Vectors & INT_Table position 
;
; INT_Table must follow immediately after INT_Vectors, with nothing in
; between the two tables for the copy above to work correctly
  
INT_Vectors

    LDR pc, INT_Table
    LDR pc, (INT_Table + 4)
    LDR pc, (INT_Table + 8)
    LDR pc, (INT_Table + 12)
    LDR pc, (INT_Table + 16)
    LDR pc, (INT_Table + 20)
    LDR pc, (INT_Table + 24)
    LDR pc, (INT_Table + 28)    
    
INT_Table

    DCD __main
    DCD handler_undefined_instr
    DCD handler_SWI
    DCD handler_prefetch_abort
    DCD handler_data_abort
    DCD 0
    DCD handler_irq
    DCD handler_fiq

SkipTable
                               
; Configure Coprocessor 15 Register 9  size and location of TCM
        LDR     r1, =0x0000000A     ; I-TCM base address 0, size = 16KB
        MCR     p15, 0, r1, c9, c1, 1   ; write control register        

        LDR     r1, =0xf7ff800C     ; D-TCM base address 0x00100000, size = 16KB
        MCR     p15, 0, r1, c9, c1, 0   ; write control register
        
; Configure Coprocessor 15 Register 1 - Control register
        MRC     p15, 0, r1, c1, c0, 0   ; read current control register value
        
; Set bits to enable TCM
        ORR     r1, r1, #(ITCM_ENABLE_946 + DTCM_ENABLE_946 )   ;enable TCM
        
; Clear bits to disable cache, protection unit and big endian
        LDR     r2, =~(ITCM_LOAD_946 + DTCM_LOAD_946 + TBIT_ENABLE_946 + ROUND_ROBIN_946 + ALTERNATE_VECTOR_946 + ICACHE_ENABLE_946 + BIG_ENDIAN_946 + DCACHE_ENABLE_946 + PROTECT_ENABLE_946)
        AND     r1, r1, r2
        MCR     p15, 0, r1, c1, c0, 0   ; write control register




;******************************************************************************
;*    Initialize stack pointer registers         
;******************************************************************************

                                            
; --- FIQ stack pointer register initialization
; Enter FIQ mode and set up the FIQ stack pointer

    MOV     r0, #Mode_FIQ:OR:I_Bit:OR:F_Bit ; Interrupts disabled
    MSR     CPSR_c, r0
    LDR     r1, =FIQ_Stack                  ; Get FIQ stack pointer
    BIC     r1, r1, #7                      ; Ensure 8-byte alignment
    MOV     sp, r1                          ; Save stack ptr in a banked   
                                            ; private copy of R13 for
                                            ; FIQ mode use only   
                                                
; --- ABT stack pointer register initialization
; Enter ABT mode and set up the ABT stack pointer

    MOV     r0, #Mode_ABT:OR:I_Bit:OR:F_Bit ; Interrupts disabled
    MSR     CPSR_c, r0
    LDR     r1, =ABT_Stack                  ; Get ABT stack pointer
    BIC     r1, r1, #7                      ; Ensure 8-byte alignment
    MOV     sp, r1                          ; Save stack ptr in a banked   
                                            ; private copy of R13 for 
                                            ; ABT mode use only 
                                            
; --- UNDEF stack pointer register initialization
; Enter UNDEF mode and set up the UNDEF stack pointer

    MOV     r0, #Mode_UNDEF:OR:I_Bit:OR:F_Bit ; Interrupts disabled
    MSR     CPSR_c, r0
    LDR     r1, =UNDEF_Stack                ; Get UNDEF stack pointer
    BIC     r1, r1, #7                      ; Ensure 8-byte alignment
    MOV     sp, r1                          ; Save stack ptr in a banked   
                                            ; private copy of R13 for     
                                            ; UNDEF mode use only

;******************************************************************************
; Initial setup of CS1 (Flash ROM) is performed in boot loader. Application-
; specific initialization follows.
;******************************************************************************

;
; The following instructions enable page mode. If the application's FROM 
; provides page mode access, using it may provide 10-20% speedup of ARM
; instruction execution.
;

;    ldr     r1,=MPMC_STA_CFG1       ; static CS1 configuration
;    ldr     r2,[r1]                 ; get current configuration
;    ldr     r3,=0x00000008          ; page mode enable bit
;    orr     r3,r3,r2                ; enable page mode
;    str     r3,[r1]
    
    LDR     r1,=MPMC_STA_WT_R1      ; static CS1 asynchronous first page-mode read,   
    LDR     r2,=0x7                 ; or non-page read, wait states, 0x7 + 1 clks = 8 wait states
    STR     r2,[r1]

    LDR     r1,=MPMC_STA_WT_P1      ; Static CS1 asynchronous page read wait states.
    LDR     r2,=0x2                 ; 0x2 + 1 = 3 wait states.
    STR     r2,[r1]                 ; 
    
    LDR     r1,=MPMC_STA_WT_T1      ; Static CS1 memory cycle turn round delay
    LDR     r2,=0x0                 ; 0x0 + 1 = 1 wait state
    STR     r2,[r1]             ; 


;******************************************************************************
;*    Intialization of DDP2230 Reference Design SDRAM Memory Device 
;*      
;*    64Mb (8MByte) SDRAM Memory Device
;*                         
;*    Attached to Chip Select 0(CS0), mapped to starting address 0xF8000000
;******************************************************************************

    IF  :DEF:DEFINE_SDRAM_INIT
    
;
; Test for prior SDRAM Initialization (eg. SW cold/warm start)
; SDRAM Initialization cannot be run more than once after PMC reset,
; otherwise SDRAM controller does not function properly 
; 
     LDR     r1, =PMC_CSZ_0         ; Address of PMC_CSZ_0 configuration register
     LDR     r2, [r1]               ; Get reserved word with sdram status init bit
     LDR     r3, =SDRAM_INIT_MASK   
     AND     r3, r3, r2             ; Clear all other status other than sdram init bit  
     CMP     r3, #2     
     BEQ     SKIP_SDRAM_INIT        ; If sdram init complete, skip sdram init
     ORR     r2, r2, #2             ; else set sdram init complete bit 
     STR     r2, [r1]               ; and store it in PMC_CSZ_0 Reserved Register bit [1]

;
; PM_Addr_21..22 are set in boot loader, as required to address 8 MB flash ROM
;

    LDR     r1,=GPIO_32_47_ENABLE   ; PM_Addr_21-23 are alternate bits on GPIO  
    LDR     r2,=0xfffffff8          ; These must be set for SDRAM
    STR     r2,[r1]

; 
; Turn off mirror of static chip enable 1 with chip enable 0 and 4
;

    LDR     r1, =MPMC_CONTROL              ; [2] = 0, normal power
    LDR     r2, =1                         ; [1] = 0, cs1 0 and 4 NOT mirrored
    STR     r2, [r1]                       ; [0] = 1, PMC enabled 

;
; Set SDRAM precharge command period
;

    LDR     r1, =MPMC_Dyn_RP               ; Address of PMC Dynamic Mem Precharge CMD Register
    LDR     r2, =SDRAM_PRECHARGE     ; 0x1   Sets value to 2 Clock Cycles = 33.4nsec 
    STR     r2, [r1]                       ; Register value is n + 1 clock cycles ie value of 
                                           ; 0 will provide 1 clk cycle
;
; Set SDRAM Active to precharge command period
;

    LDR     r1, =MPMC_Dyn_RAS               ; Address of PMC Dynamic Tras CMD Register
    LDR     r2, =SDRAM_ACTIVE_TO_PRECHARGE  ;  0x2      Set value to 3 Clock Cycles = 50nsec 
    STR     r2, [r1]

;
; Set SDRAM Last Data Out to Active Command time
;

    LDR     r1, =MPMC_Dyn_APR               ; Address of PMC Dynamic Tapr Register
    LDR     r2, =SDRAM_LAST_DATA_TO_ACTIVE  ; 0x0  Set value to 4 Clock Cycles = 67nsec 
    STR     r2, [r1]

;
; Set SDRAM Data-In to Active Command time 
;

    LDR     r1, =MPMC_Dyn_DAL               ; Address of PMC Dynamic Tdal Register
    LDR     r2, =SDRAM_DATA_IN_TO_ACTIVE    ; 0x5         Sets value to 5 Clock Cycles 
    STR     r2, [r1]

;
; Set SDRAM Write recovery time
;

    LDR     r1, =MPMC_Dyn_WR                ; Address of PMC Dynamic Twr Register
    LDR     r2, =SDRAM_WRITE_RECOVERY       ; 0x1         Sets value to 2 Clock Cycles 
    STR     r2, [r1]

;
; Set SDRAM Active to Active Command period
;

    LDR     r1, =MPMC_Dyn_RC                ; Address of PMC Dynamic Trc Register
    LDR     r2, =SDRAM_ACTIVE_TO_ACTIVE     ; 0x4         Sets value to 5 Clock Cycles = 83nsec 
    STR     r2, [r1]

;
; Set SDRAM Auto Refresh period
;

    LDR     r1, =MPMC_Dyn_RFC               ; Address of PMC Dynamic Trfc Register
    LDR     r2, =SDRAM_AUTO_REFRESH         ; 0x4      Sets value to 5 Clock Cycles = 83nsec 
    STR     r2, [r1]

;
; Set SDRAM Exit Self-Refresh to Active Command Time
;

    LDR     r1, =MPMC_Dyn_XSR               ; Address of PMC Dynamic Txsr Register
    LDR     r2, =SDRAM_EXIT_SLF_REF_TO_ACT  ; 0x5         Sets value to 5 Clock Cycles = 83nsec 
    STR     r2, [r1]

;
; Set SDRAM Active A Bank to Active B Bank latency
;

    LDR     r1, =MPMC_Dyn_RRD               ; Address of PMC Dynamic Trrd Register
    LDR     r2, =SDRAM_ACTA_TO_ACTB         ; 0x1         Sets value to 2 Clock Cycle = 33.4nsec 
    STR     r2, [r1]

;
; Set SDRAM Load Mode Register to Active Command Time
;

    LDR     r1, =MPMC_Dyn_MRD               ; Address of PMC Dynamic Trrd Register
    LDR     r2, =SDRAM_TMRD                 ; 0x1               Sets value to 2 Clock Cycles 
    STR     r2, [r1]

;    
; Set SDRAM Dynamic memory read configuration register  
;

    LDR     r1, =MPMC_Dyn_ReadCfg           ; command delayed strategy, using
    LDR     r2, =1                          ; MPMCCLKDELAY (command delayed
    STR     r2, [r1]                        ; clock out not delayed

;
; SDRAM Initialization Procedure from ARM Primecell PL172 Tech Spec page 6-58   
;
; Step 1
; Wait for 100 usecs after power-up 
; --------------------------------------------------------------------------------

    LDR     r1, =POWERUP_WAIT   
5   SUB     r1, r1, #1
    CMP     r1,#0
    BNE     %B5   

; Step 2
; Set SDRAM Initialization to NOP in Dynamic Control Register
; This issues a NOP command to SDRAM 
; --------------------------------------------------------------------------------

    LDR     r1, =MPMC_Dyn_Ctl ; Address of PMC SDRAM Control Register
    LDR     r2, =0x00000183   ; Re-apply POR defaults & issue NOP command 
    STR     r2, [r1]