📄 init.s
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;******************************************************************************
;* TEXAS INSTRUMENTS PROPRIETARY INFORMATION
;*
;* (c) Copyright, Texas Instruments Incorporated, 2002-2006.
;* All Rights Reserved.
;*
;* Property of Texas Instruments Incorporated. Restricted Rights -
;* Use, duplication, or disclosure is subject to restrictions set
;* forth in TI's program license agreement and associated documentation.
;*
;******************************************************************************/
;
;**********************************************************************
;*
;* init.s: ARM946 application boot code.
;* Initializes memory, sets up exception vectors,
;* and branches to application via the function named
;* "C_Entry".
;*
;**********************************************************************
;******************************************************************************
;* ARM946E-S Status Register Bit Defintions
;******************************************************************************
PRESERVE8
; Arm Processor Mode Definitions
Mode_MASK EQU 0x1F ; mask for mode bits
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UNDEF EQU 0x1B
Mode_SYS EQU 0x1F
EXPORT Mode_USR
EXPORT Mode_MASK
; Control Bit Definitions
I_Bit EQU 0x80 ; Enables/Disables IRQ when bit is cleared/set
F_Bit EQU 0x40 ; Enables/Disables FIQ when bit is cleared/set
T_Bit EQU 0x20 ; Bit Set = Thumb Mode, Bit Cleared = ARM Mode
EXPORT I_Bit
EXPORT F_Bit
EXPORT T_Bit
;******************************************************************************
;* DDP2230 ASIC Stack Definitions
;*
;* Internal 16 KByte D-TCM for all ARM Mode Stacks & RW/ZI Data
;*
;******************************************************************************
IF :DEF: DEFINE_IRAM_STACK
Stack_Limit EQU 0xF7FFFFF8 ; Top of application space in DTCM,
; minus two reserved 32bit words
ENDIF
IF :DEF: DEFINE_SDRAM_STACK
Stack_Limit EQU 0xF87FFFF8 ; Top of application space in SDRAM,
; minus two reserved 32bit words
ENDIF
IF :DEF: DEFINE_SRAM_STACK
Stack_Limit EQU 0xFB07FFF8 ; Top of application space in SRAM,
; minus two reserved 32bit words
ENDIF
;************************************************************************************
; s t a c k s p a c e
;
; All system stacks are overlaid on the same memory. This is feasible for the
; following reasons:
;
; SVC_Stack: The SVC stack is used at startup and is sized appropriately. It is
; used only until the RTOS is started, so the IRQ stack is overlaid
; on the same memory.
;
; IRQ_Stack: Interrupts are not enabled until the RTOS is started and the first
; RTOS task is in execution - At this time, the SVC stack is no longer
; in use.
;
; USR_Stack: The application runs in supervisor mode; the user stack is unused.
;
; FIQ_Stack: The application does not use FIQs; the FIQ stack is unused.
;
; ABT_Stack:
; UNDEF_Stack: Memory aborts and undefined instruction exceptions can occur. The
; occurance causes an application restart - No attempt is made to
; recover and continue operation. Interrupts are disabled and remain
; disabled during exception handling, thus the interrupt stack will
; not be used during exception handling.
;************************************************************************************
Sys_Stack_Size EQU 512
SVC_Stack EQU Stack_Limit
IRQ_Stack EQU Stack_Limit
USR_Stack EQU Stack_Limit
FIQ_Stack EQU Stack_Limit
ABT_Stack EQU Stack_Limit
UNDEF_Stack EQU Stack_Limit
HEAP_End EQU SVC_Stack - Sys_Stack_Size
EXPORT IRQ_Stack
EXPORT SVC_Stack
EXPORT HEAP_End
EXPORT Stack_Limit
;**********************************************************************
;* Bit Definitions
;**********************************************************************
BIT0 EQU 0x00000001
BIT1 EQU 0x00000002
BIT2 EQU 0x00000004
BIT3 EQU 0x00000008
BIT4 EQU 0x00000010
BIT5 EQU 0x00000020
BIT6 EQU 0x00000040
BIT7 EQU 0x00000080
BIT8 EQU 0x00000100
BIT9 EQU 0x00000200
BIT10 EQU 0x00000400
BIT11 EQU 0x00000800
BIT12 EQU 0x00001000
BIT13 EQU 0x00002000
BIT14 EQU 0x00004000
BIT15 EQU 0x00008000
BIT16 EQU 0x00010000
BIT17 EQU 0x00020000
BIT18 EQU 0x00040000
BIT19 EQU 0x00080000
BIT20 EQU 0x00100000
BIT21 EQU 0x00200000
BIT22 EQU 0x00400000
BIT23 EQU 0x00800000
BIT24 EQU 0x01000000
BIT25 EQU 0x02000000
BIT26 EQU 0x04000000
BIT27 EQU 0x08000000
BIT28 EQU 0x10000000
BIT29 EQU 0x20000000
BIT30 EQU 0x40000000
BIT31 EQU 0x80000000
; These definitions are for region size of 946E-S
; Binary representation with lsb being the enable bit
REGIONSIZE4K EQU 2_010110
REGIONSIZE8K EQU 2_011000
REGIONSIZE16K EQU 2_011010
REGIONSIZE32K EQU 2_011100
REGIONSIZE64K EQU 2_011110
REGIONSIZE128K EQU 2_100000
REGIONSIZE256K EQU 2_100010
REGIONSIZE512K EQU 2_100100
REGIONSIZE1MB EQU 2_100110
REGIONSIZE2MB EQU 2_101000
REGIONSIZE4MB EQU 2_101010
REGIONSIZE8MB EQU 2_101100
REGIONSIZE16MB EQU 2_101110
REGIONSIZE32MB EQU 2_110000
REGIONSIZE64MB EQU 2_110010
REGIONSIZE128MB EQU 2_110100
REGIONSIZE256MB EQU 2_110110
REGIONSIZE512MB EQU 2_111000
REGIONSIZE1GB EQU 2_111010
REGIONSIZE2GB EQU 2_111100
REGIONSIZE4GB EQU 2_111110
P_REGION_DISABLE EQU 2_0
P_REGION_ENABLE EQU 2_1
;******************************************************************************
;* ARM946E-S Co-Processor Register 15 control register bit definitions
;******************************************************************************
ITCM_LOAD_946 EQU BIT19 ; enable load I-TCM
ITCM_ENABLE_946 EQU BIT18 ; enable I-TCM
DTCM_LOAD_946 EQU BIT17 ; enable load D-TCM
DTCM_ENABLE_946 EQU BIT16 ; enable D-TCM
TBIT_ENABLE_946 EQU BIT15 ; disable loading TBIT
ROUND_ROBIN_946 EQU BIT14 ; round robin replacement
ALTERNATE_VECTOR_946 EQU BIT13 ; vectors set high (0xFFFF0000)
ICACHE_ENABLE_946 EQU BIT12 ; program cache enable/disable
BIG_ENDIAN_946 EQU BIT7 ; big endian
DCACHE_ENABLE_946 EQU BIT2 ; data cache enable/disable
PROTECT_ENABLE_946 EQU BIT0 ; projection unit enable/disable
;******************************************************************************
;* PMC definitions for SDRAM etc
;******************************************************************************
MPMC_CONTROL EQU 0x11021000 ;
;PMC SDRAM register definitions ; Dyn Mem Auto Refresh Period Reg
MPMC_Dyn_Ctl EQU 0x11021020 ; Dyn Mem Control Register
MPMC_Dyn_Refr EQU 0x11021024 ; Dyn Mem Refresh Timer
MPMC_Dyn_ReadCfg EQU 0x11021028 ; Dyn Mem Read Config
MPMC_Dyn_RP EQU 0x11021030 ; Dyn Mem Precharge CMD Period Reg
MPMC_Dyn_RAS EQU 0x11021034 ; Dyn Mem Precharge CMD Period Reg
MPMC_Dyn_SREX EQU 0x11021038 ; Dyn Mem Self-Rfrsh Exit Time Reg
MPMC_Dyn_APR EQU 0x1102103C ; Dyn Mem Last Data Out-Active Reg
MPMC_Dyn_DAL EQU 0x11021040 ; Dyn Mem Data-In to Active CMD Reg
MPMC_Dyn_WR EQU 0x11021044 ; Dyn Mem Write Recovery Time Reg
MPMC_Dyn_RC EQU 0x11021048 ; Dyn Mem Active-Active CMD Per Reg
MPMC_Dyn_RFC EQU 0x1102104C ; Dyn Mem Auto Refresh Period Reg
MPMC_Dyn_XSR EQU 0x11021050 ; Dyn Mem Auto Refresh Period Reg
MPMC_Dyn_RRD EQU 0x11021054 ; Dyn Mem Act A Bank- Act B Bank Reg
MPMC_Dyn_MRD EQU 0x11021058 ; Dyn Mem Load Mode to Act CMD time Reg
MPMC_Dyn_Cfg0 EQU 0x11021100 ; Dynamic Mem Config Register
MPMC_Dyn_RC0 EQU 0x11021104 ; Dynamic Mem RAS/CAS Delay Reg
MPMC_Dyn_Cfg3 EQU 0x11021160 ; Dynamic Mem Config Register
MPMC_Dyn_RC3 EQU 0x11021164 ; Dynamic Mem RAS/CAS Delay Reg
MPMC_STA_CFG0 EQU 0x11021200 ; STATIC MEMORY CONFIGURATION REGISTER
MPMC_STA_WT_E0 EQU 0x11021204 ; STATIC MEMORY WRITE ENABLE DELAY
MPMC_STA_O_E0 EQU 0x11021208 ; STATIC MEMORY OUTPUT ENABLE DELAY
MPMC_STA_WT_R0 EQU 0x1102120C ; STATIC MEMORY MEMORY READ DELAY
MPMC_STA_WT_P0 EQU 0x11021210 ; STATIC MEMORY PAGE MODE READ DELAY
MPMC_STA_WT_W0 EQU 0x11021214 ; STATIC MEMORY WRITE DELAY
MPMC_STA_WT_T0 EQU 0x11021218 ; STATIC MEMORY TURN ROUND DELAY
MPMC_STA_CFG1 EQU 0x11021220 ; STATIC MEMORY CONFIGURATION REGISTER
MPMC_STA_WT_E1 EQU 0x11021224 ; STATIC MEMORY WRITE ENABLE DELAY
MPMC_STA_O_E1 EQU 0x11021228 ; STATIC MEMORY OUTPUT ENABLE DELAY
MPMC_STA_WT_R1 EQU 0x1102122C ; STATIC MEMORY MEMORY READ DELAY
MPMC_STA_WT_P1 EQU 0x11021230 ; STATIC MEMORY PAGE MODE READ DELAY
MPMC_STA_WT_W1 EQU 0x11021234 ; STATIC MEMORY WRITE DELAY
MPMC_STA_WT_T1 EQU 0x11021238 ; STATIC MEMORY TURN ROUND DELAY
MPMC_STA_CFG2 EQU 0x11021240 ; STATIC MEMORY CONFIGURATION REGISTER
MPMC_STA_WT_E2 EQU 0x11021244 ; STATIC MEMORY WRITE ENABLE DELAY
MPMC_STA_O_E2 EQU 0x11021248 ; STATIC MEMORY OUTPUT ENABLE DELAY
MPMC_STA_WT_R2 EQU 0x1102124C ; STATIC MEMORY MEMORY READ DELAY
MPMC_STA_WT_P2 EQU 0x11021250 ; STATIC MEMORY PAGE MODE READ DELAY
MPMC_STA_WT_W2 EQU 0x11021254 ; STATIC MEMORY WRITE DELAY
MPMC_STA_WT_T2 EQU 0x11021258 ; STATIC MEMORY TURN ROUND DELAY
MPMC_STA_CFG3 EQU 0x11021260 ; STATIC MEMORY CONFIGURATION REGISTER
MPMC_STA_WT_E3 EQU 0x11021264 ; STATIC MEMORY WRITE ENABLE DELAY
MPMC_STA_O_E3 EQU 0x11021268 ; STATIC MEMORY OUTPUT ENABLE DELAY
MPMC_STA_WT_R3 EQU 0x1102126C ; STATIC MEMORY MEMORY READ DELAY
MPMC_STA_WT_P3 EQU 0x11021270 ; STATIC MEMORY PAGE MODE READ DELAY
MPMC_STA_WT_W3 EQU 0x11021274 ; STATIC MEMORY WRITE DELAY
MPMC_STA_WT_T3 EQU 0x11021278 ; STATIC MEMORY TURN ROUND DELAY
MPMCITCR EQU 0x11021F00 ; TEST CONTROL REGISTER
MPMCITIP EQU 0x11021F20 ; TEST INPUT REGISTER
MPMCITOP EQU 0x11021F40 ; TEST OUTPUT REGISTER
MPMC_PERPH_ID4 EQU 0x11021FD0 ; PERIPHERAL ID BITS (39 - 32)
MPMC_PERPH_ID5 EQU 0x11021FD4 ; PERIPHERAL RESERVED
MPMC_PERPH_ID6 EQU 0x11021FD8 ; PERIPHERAL RESERVED
MPMC_PERPH_ID7 EQU 0x11021FDC ; PERIPHERAL RESERVED
MPMC_PERPH_ID0 EQU 0x11021FE0 ; PERIPHERAL ID BITS (7 - 0)
MPMC_PERPH_ID1 EQU 0x11021FE4 ; PERIPHERAL ID BITS (15 - 8)
MPMC_PERPH_ID2 EQU 0x11021FE8 ; PERIPHERAL ID BITS (23 - 16)
MPMC_PERPH_ID3 EQU 0x11021FEC ; PERIPHERAL ID BITS (31 - 24)
MPMC_CELL_ID0 EQU 0x11021FF0 ; PRIMECELL ID BITS (7-0)
MPMC_CELL_ID1 EQU 0x11021FF4 ; PRI ; Dyn Mem Auto Refresh Period Reg
MPMC_CELL_ID2 EQU 0x11021FF8 ; PRIMECELL ID BITS (23-16)
MPMC_CELL_ID3 EQU 0x11021FFC ; PRIMECELL ID BITS (31-24)
;
; Initialization values for Micron MT48LC4M16A2 SDRAM
;
IF {FALSE}
SDRAM_PRECHARGE EQU 0x1 ; PRECHARGE IN CLOCKS (N + 1) -75 part 20ns
SDRAM_ACTIVE_TO_PRECHARGE EQU 0x2 ; ACTIVE TO PRECHARGE MIN 44NS
SDRAM_LAST_DATA_TO_ACTIVE EQU 0x0
SDRAM_DATA_IN_TO_ACTIVE EQU 0x5 ; DATA IN TO ACTIVE COMMAND 5 TCLK
SDRAM_WRITE_RECOVERY EQU 0x1 ; WRITE RECOVERY TIME 1 CLK + 7.5 NS
SDRAM_ACTIVE_TO_ACTIVE EQU 0x4 ; ACTIVE TO ACTIVE 66NS
SDRAM_AUTO_REFRESH EQU 0x4 ; AUTO REFRESH 66NS
SDRAM_EXIT_SLF_REF_TO_ACT EQU 0x5 ; AUTO REFRESH PERIOD 66NS
SDRAM_ACTA_TO_ACTB EQU 0x1 ; ACTIVE BANK A TO ACTIVE BANK B 15NS
SDRAM_TMRD EQU 0x1 ; LOAD MODE REG COMMAND TO ACT OR REFRESH COMMAND 3 CLKS
SDRAM_SELF_REFRESH_EXIT EQU 0x1 ; SELFREFRESH TIME
SDRAM_MODE EQU 0xF8019800 ; Micron Mode definition see step 10 below
ENDIF
;
; Initialization values for SAMSUNG K4S641632K SDRAM
;
IF {TRUE}
SDRAM_PRECHARGE EQU 0x0 ; (RP)PRECHARGE IN CLOCKS (N + 1) -75 part 20ns
SDRAM_ACTIVE_TO_PRECHARGE EQU 0x0 ; (RAS)ACTIVE TO PRECHARGE MIN 44NS
SDRAM_LAST_DATA_TO_ACTIVE EQU 0x0 ; (APR)
SDRAM_DATA_IN_TO_ACTIVE EQU 0x3 ; (DAL)DATA IN TO ACTIVE COMMAND 5 TCLK
SDRAM_WRITE_RECOVERY EQU 0x1 ; (WR)WRITE RECOVERY TIME 1 CLK + 7.5 NS
SDRAM_ACTIVE_TO_ACTIVE EQU 0x1 ; (RC)ACTIVE TO ACTIVE 66NS
SDRAM_AUTO_REFRESH EQU 0x1 ; (RFC)AUTO REFRESH 66NS
SDRAM_EXIT_SLF_REF_TO_ACT EQU 0x1 ; (XSR)AUTO REFRESH PERIOD 66NS
SDRAM_ACTA_TO_ACTB EQU 0x0 ; (RRD)ACTIVE BANK A TO ACTIVE BANK B 15NS
SDRAM_TMRD EQU 0x2 ; (MRD)LOAD MODE REG COMMAND TO ACT OR REFRESH COMMAND 3 CLKS
SDRAM_SELF_REFRESH_EXIT EQU 0x1 ; SELFREFRESH TIME
SDRAM_MODE EQU 0xF8011800 ; Mode definition see step 10 below
ENDIF
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