tvp7001.c

IT projecotr reference design.

 * @param  *clamp_placement  - I - storage for clamp_placement value
 *
 * @return PASS													<BR>
 *		   ADC_FUNCTION_NOT_SUPPORTED							<BR>
 *		   ADC_I2C_DRIVER_ERROR									<BR>
 * 		   ADC_I2C_DRIVER_TERMINAL_ERROR  						<BR> 
 *		   ADC_RTA_SEM_IN_USE									<BR>
 *		   ADC_RTA_ERROR
 */
{
	int08 status;
	uint08 data;

	status = ADC_GetADCByte(ADC_CLAMP_PLACEMENT, &data);
	if (status == PASS)
	{
		*clamp_placement = (uint16)data;
	}        
	
	return status;
}

int08 ADC_GetClampPlacementLimits(ADC_LimitStruct *limits)
/**
 * Gets the ADC limits of the clamp placement value.
 *
 * @param  *limits - I - pointer to struct containing limit values.
 *
 * @return PASS													<BR>
 *         ADC_FIELD_LIMITS_UNSPECIFIED
 */
{       
	int08 status;  
   	ADC_FieldLimitsStruct field_limits;

    status = ADC_GetLimits(ADC_CLAMP_PLACEMENT_LIMITS, &field_limits);
    if (status == PASS) *limits = field_limits.Limits;
 	return status;
}

int08 ADC_SetClampDuration(uint16 clamp_duration)
/**
 * Sets the ADC clamp duration value.
 *
 * This value defines the duration of the clamp signal in
 * pixel periods. This register is valid only when the ADC
 * is configured for internal clamping.
 *
 * NOTE:														<BR>
 * The AutoLock algorithm will sometimes call this function 
 * during source detection. OEM supplied ADC drivers must
 * implement this function and implement it so the argument
 * represents the duration of the clamp signal in pixel periods. 
 * 
 * @param  clamp_duration - I - clamp duration
 *
 * @return PASS													<BR>
 *   	   ADC_FUNCTION_NOT_SUPPORTED							<BR>
 *   	   ADC_FIELD_LIMITS_UNSPECIFIED							<BR>
 *         ADC_VALUE_OOR_MIN									<BR>
 *         ADC_VALUE_OOR_MAX									<BR>
 *         ADC_I2C_DRIVER_ERROR									<BR>
 * 		   ADC_I2C_DRIVER_TERMINAL_ERROR  						<BR> 
 *         ADC_RTA_SEM_IN_USE									<BR>
 *         ADC_RTA_ERROR		   		    
 */
{
    int08 status;
    uint08 alc_placement;

	/* Do this because ADC_SetADCByte() will not range check 16 bit input */
	if (clamp_duration > 0xFF)
	{
		return ADC_VALUE_OOR_MAX;
	}	
 
	status = ADC_SetADCByte(ADC_CLAMP_DURATION, (uint08)clamp_duration);        

//    return status;
	
	if (status != PASS) return status;

    alc_placement = ADC_Registers[5] + ADC_Registers[6];
	return ADC_SetADCByte(ADC_ALC_PLACEMENT, alc_placement);                        	
}

int08 ADC_GetClampDuration(uint16 *clamp_duration)
/**
 * Gets the ADC clamp duration value.
 *
 * @param  *offset  - I - storage for clamp_duration value
 *
 * @return PASS													<BR>
 *		   ADC_FUNCTION_NOT_SUPPORTED							<BR>
 *		   ADC_I2C_DRIVER_ERROR									<BR>
 * 		   ADC_I2C_DRIVER_TERMINAL_ERROR  						<BR> 
 *		   ADC_RTA_SEM_IN_USE									<BR>
 *		   ADC_RTA_ERROR
 */
{ 
	int08 status;
	uint08 data;

	status = ADC_GetADCByte(ADC_CLAMP_DURATION, &data);
	if (status == PASS)
	{
		*clamp_duration = (uint16)data;
	}        
	
	return status;	
}

int08 ADC_GetClampDurationLimits(ADC_LimitStruct *limits)
/**
 * Gets the ADC limits of the clamp duration value.
 *
 * @param  *limits - I - pointer to struct containing limit values.
 *
 * @return PASS													<BR>
 *         ADC_FIELD_LIMITS_UNSPECIFIED
 */
{     
	int08 status;
	ADC_FieldLimitsStruct field_limits;

    status = ADC_GetLimits(ADC_CLAMP_DURATION_LIMITS, &field_limits);
    if (status == PASS) *limits = field_limits.Limits;    
    return status;
}

/*****************************************************************************/
/* HSYNC Pulse Width  ********************************************************/
/*****************************************************************************/

int08 ADC_SetHsyncPulseWidth(uint16 hsync_pulse_width)
/**
 * Sets the ADC HSYNC pulse width.
 *
 * This value adjusts the width of the HSYNC pulse in 
 * units of pixel clock.
 *
 * @param  hsync_pulse_width - I - width of HSYNC pulse in pixel clocks
 *
 * @return PASS													<BR>
 *   	   ADC_FUNCTION_NOT_SUPPORTED							<BR>
 *   	   ADC_FIELD_LIMITS_UNSPECIFIED							<BR>
 *         ADC_VALUE_OOR_MIN									<BR>
 *         ADC_VALUE_OOR_MAX									<BR>
 *         ADC_I2C_DRIVER_ERROR									<BR>
 * 		   ADC_I2C_DRIVER_TERMINAL_ERROR  						<BR> 
 *         ADC_RTA_SEM_IN_USE									<BR>
 *         ADC_RTA_ERROR		   		    
 */
{ 
	/* Do this because ADC_SetADCByte() will not range check 16 bit input */
	if (hsync_pulse_width > 0xFF)
	{
		return ADC_VALUE_OOR_MAX;
	}	

	return ADC_SetADCByte(ADC_HSYNC_PULSEWIDTH, (uint08)hsync_pulse_width);            
}

int08 ADC_GetHsyncPulseWidth(uint16 *hsync_pulse_width)
/**
 * Gets the ADC HSYNC pulse width.
 *
 * @param  *hsync_pulse_width - I - pointer to HSYNC pulse width
 *
 * @return PASS													<BR>
 *		   ADC_FUNCTION_NOT_SUPPORTED							<BR>
 *		   ADC_I2C_DRIVER_ERROR									<BR>
 * 		   ADC_I2C_DRIVER_TERMINAL_ERROR  						<BR> 
 *		   ADC_RTA_SEM_IN_USE									<BR>
 *		   ADC_RTA_ERROR
 */
{ 	
	int08 status;
	uint08 data;

	status = ADC_GetADCByte(ADC_HSYNC_PULSEWIDTH, &data);
	if (status == PASS)
	{
		*hsync_pulse_width = (uint16)data;
	}        
	
	return status;	
}

int08 ADC_GetHsyncPulseWidthLimits(ADC_LimitStruct *limits)
/**
 * Gets the ADC limits of the HSYNC pulse width.
 *
 * @param  *limits - I - pointer to struct containing limit values.
 *
 * @return PASS													<BR>
 *         ADC_FIELD_LIMITS_UNSPECIFIED
 */
{     
	int08 status;
  	ADC_FieldLimitsStruct field_limits;

    status = ADC_GetLimits(ADC_HSYNC_PULSE_WIDTH_LIMITS, &field_limits);
    if (status == PASS) *limits = field_limits.Limits;
    return status;
}

/*****************************************************************************/
/* General Control  **********************************************************/
/*****************************************************************************/

int08 ADC_SetOutputPortWidth(uint08 output_width_is_48)
/**
 * Sets the ADC output port width.
 *
 * When 0 - All data goes to Port A (24 bit wide)				<BR>
 * When 1 - Pixels alternate between Port A and Port B (48 bit wide).
 *
 * @param  output_width_is_48 - I - output port select value 
 *
 * @return PASS													<BR>
 *   	   ADC_FUNCTION_NOT_SUPPORTED							<BR>
 *   	   ADC_FIELD_LIMITS_UNSPECIFIED							<BR>
 *         ADC_VALUE_OOR_MIN									<BR>
 *         ADC_VALUE_OOR_MAX									<BR>
 *         ADC_I2C_DRIVER_ERROR									<BR>
 * 		   ADC_I2C_DRIVER_TERMINAL_ERROR  						<BR> 
 *         ADC_RTA_SEM_IN_USE									<BR>
 *         ADC_RTA_ERROR		   		    
 */
{     
	return ADC_SetADCByte(ADC_OUTPUT_WIDTH, output_width_is_48);
}

int08 ADC_GetOutputPortWidth(uint08 *output_width_is_48)
/**
 * Gets the ADC output port width.
 *
 * When 0 - All data goes to Port A (24 bit wide)				<BR>
 * When 1 - Pixels alternate between Port A and Port B (48 bit wide).
 *
 * @param  *output_width_is_48 - I - pointer to output port select value 
 *
 * @return PASS													<BR>
 *		   ADC_FUNCTION_NOT_SUPPORTED							<BR>
 *		   ADC_I2C_DRIVER_ERROR									<BR>
 * 		   ADC_I2C_DRIVER_TERMINAL_ERROR  						<BR> 
 *		   ADC_RTA_SEM_IN_USE									<BR>
 *		   ADC_RTA_ERROR
 */
{ 
    return ADC_GetADCByte(ADC_OUTPUT_WIDTH, output_width_is_48);
}
    
int08 ADC_SetDVIOutputPortWidth(uint08 output_width_is_48)
/**
 * Sets the DVI output port width.
 *
 * When 0 - All data goes to Port A (24 bit wide)				<BR>
 * When 1 - Pixels alternate between Port A and Port B (48 bit wide).
 *
 * @param  output_width_is_48 - I - output port select value 
 *
 * @return PASS													<BR>
 *   	   ADC_FUNCTION_NOT_SUPPORTED							<BR>
 *   	   ADC_FIELD_LIMITS_UNSPECIFIED							<BR>
 *         ADC_VALUE_OOR_MIN									<BR>
 *         ADC_VALUE_OOR_MAX									<BR>
 *         ADC_I2C_DRIVER_ERROR									<BR>
 * 		   ADC_I2C_DRIVER_TERMINAL_ERROR  						<BR> 
 *         ADC_RTA_SEM_IN_USE									<BR>
 *         ADC_RTA_ERROR		   		    
 */
{     
	return ADC_SetADCByte(ADC_DVI_OUTPUT_WIDTH, output_width_is_48);
}

int08 ADC_GetDVIOutputPortWidth(uint08 *output_width_is_48)
/**
 * Gets the DVI output port width.
 *
 * When 0 - All data goes to Port A (24 bit wide)				<BR>
 * When 1 - Pixels alternate between Port A and Port B (48 bit wide).
 *
 * @param  *output_width_is_48 - I - pointer to output port select value 
 *
 * @return PASS													<BR>
 *		   ADC_FUNCTION_NOT_SUPPORTED							<BR>
 *		   ADC_I2C_DRIVER_ERROR									<BR>
 * 		   ADC_I2C_DRIVER_TERMINAL_ERROR  						<BR> 
 *		   ADC_RTA_SEM_IN_USE									<BR>
 *		   ADC_RTA_ERROR
 */
{ 
    return ADC_GetADCByte(ADC_DVI_OUTPUT_WIDTH, output_width_is_48);
}
    
int08 ADC_GetOutputMode(uint08 *simultaneous_data_on_ports)
/**
 * Gets the ADC output timing select value.
 *
 * When 0 - Data alternates between port A & B. Port A data is available on the
 *          rising edge of DATACK and port B data is available on the rising
 *          edge of ~DATACK (falling edge of DATACK).			<BR>
 * When 1 - Port A data and DATACK is delayed half of a DATACK period and 
 *          data from both Port A and Port B is available on the DATACK
 *          rising edge.
 * This register is ignored when the ADC is configured for single
 * port output (Output Port Select = 0). 
 *
 * @param  *simultaneous_data_on_ports - I - pointer to output timing select value
 *
 * @return PASS													<BR>
 *		   ADC_FUNCTION_NOT_SUPPORTED							<BR>
 *		   ADC_I2C_DRIVER_ERROR									<BR>
 * 		   ADC_I2C_DRIVER_TERMINAL_ERROR  						<BR> 
 *		   ADC_RTA_SEM_IN_USE									<BR>
 *		   ADC_RTA_ERROR
 */
{ 
    return ADC_GetADCByte(ADC_OUTPUT_MODE, simultaneous_data_on_ports);    
}

int08 ADC_SetOutputHSYNCPolarity(uint08 active_high)
/**
 * Sets the polarity of the HSYNC signal output from the ADC.
 *
 * When 0 - The polarity of the input HSYNC signal is negative.	<BR>
 * When 1 - The polarity of the input HSYNC signal is positive.
 *
 * @param  active_high - I - HSYNC signal polarity indicator
 *
 * @return PASS													<BR>
 *   	   ADC_FUNCTION_NOT_S