📄 tvp7001.c
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/****************************************************************************/
/* TEXAS INSTRUMENTS PROPRIETARY INFORMATION */
/* */
/* (c) Copyright, Texas Instruments Incorporated, 2005-2007. */
/* All Rights Reserved. */
/* */
/* Property of Texas Instruments Incorporated. Restricted Rights - */
/* Use, duplication, or disclosure is subject to restrictions set */
/* forth in TI's program license agreement and associated documentation. */
/****************************************************************************/
#include "common.h"
#include "i2c.h"
#include "int.h"
#include "TVP7001.h"
#include "rta_tsk.h"
#include "rta_sem.h"
#include "rta_pub.h"
#ifdef __ADC_TVP7001
#ifndef DOXYGEN_SHOULD_SKIP_THIS
/*****************************************************************************/
/* Global variables ********************************************************/
/*****************************************************************************/
/*****************************************************************************/
/* Private typedefs **********************************************************/
/*****************************************************************************/
/* These enumerated types define the various functions */
/* that may be found on an ADC. New functions may be */
/* added to the bottom of the list. */
typedef enum ADC_FunctionEnum
{
ADC_CHIP_REVISION,
ADC_PLL_MSB,
ADC_PLL_LSB,
ADC_VCO,
ADC_CHARGE_PUMP,
ADC_PHASE,
ADC_CLAMP_PLACEMENT,
ADC_CLAMP_DURATION,
ADC_HSYNC_PULSEWIDTH,
ADC_RED_GAIN,
ADC_GREEN_GAIN,
ADC_BLUE_GAIN,
ADC_RED_OFFSET,
ADC_GREEN_OFFSET,
ADC_BLUE_OFFSET,
ADC_OUTPUT_WIDTH,
ADC_OUTPUT_MODE,
ADC_OUTPUT_PHASE,
ADC_HSYNC_OUT_POLARITY,
ADC_VSYNC_OUT_INVERT,
ADC_HSYNC_INPUT_POLARITY,
ADC_COAST_INPUT_POLARITY,
ADC_CLAMP_SOURCE,
ADC_CLAMP_POLARITY,
ADC_PIXEL_CLOCK_SOURCE,
ADC_RED_CLAMP_SELECT,
ADC_GREEN_CLAMP_SELECT,
ADC_BLUE_CLAMP_SELECT,
ADC_DVI_CLOCK_INVERT,
ADC_DVI_OUTPUT_WIDTH,
ADC_TRISTATE_OUTPUTS,
ADC_SYNC_DETECT_PIN_POLARITY,
ADC_HSYNC_ACTIVITY_STATUS,
ADC_SOG_ACTIVITY_STATUS,
ADC_VSYNC_ACTIVITY_STATUS,
ADC_DVI_CLOCK_ACTIVITY_STATUS,
ADC_ACTIVE_IF_STATUS,
ADC_ACTIVE_HSYNC_STATUS,
ADC_ACTIVE_VSYNC_STATUS,
ADC_ACTIVE_IF_OVERRIDE,
ADC_ACTIVE_IF_SELECT,
ADC_ACTIVE_HSYNC_OVERRIDE,
ADC_ACTIVE_HSYNC_SELECT,
ADC_ACTIVE_VSYNC_OVERRIDE,
ADC_ACTIVE_VSYNC_SELECT,
ADC_COAST_SOURCE,
ADC_CHIP_POWER,
ADC_SYNC_SEPARATOR_THRESHOLD,
ADC_SCAN_ENABLE,
ADC_COAST_POLARITY_OVERRIDE,
ADC_HSYNC_IN_POLARITY_OVERRIDE,
ADC_HSYNC_IN_POLARITY_STATUS,
ADC_VSYNC_IN_POLARITY_STATUS,
ADC_COAST_IN_POLARITY_STATUS,
ADC_SOG_SLICER_THRESHOLD,
ADC_PRE_COAST,
ADC_POST_COAST,
ADC_OUTPUT_FORMAT,
ADC_INPUT_MUX_CONTROL,
ADC_INPUT_BANDWIDTH,
ADC_HDCP_MASTER_SERIAL_PORT,
ADC_RED_TARGET_CODE,
ADC_GREEN_TARGET_CODE,
ADC_BLUE_TARGET_CODE,
ADC_AUTO_OFFSET,
ADC_HOLD_AUTO_OFFSET,
ADC_UPDATE_MODE,
ADC_MACROVISION_SRC_SEL,
ADC_VSYNC_IN_POLARITY_OVERRIDE,
ADC_VSYNC_INPUT_POLARITY,
ADC_INPUT_SOG_SELECT,
ADC_INPUT_RED_SELECT,
ADC_INPUT_GREEN_SELECT,
ADC_INPUT_BLUE_SELECT,
ADC_INPUT_SELECT,
ADC_INPUT_SELECT2_BIT7,
ADC_INPUT_HSYNC_SELECT,
ADC_INPUT_VSYNC_SELECT,
ADC_SOG_CLAMP,
ADC_BLUE_COARSE_GAIN,
ADC_GREEN_COARSE_GAIN,
ADC_RED_COARSE_GAIN,
ADC_BLUE_FINE_OFFSET_LSB,
ADC_GREEN_FINE_OFFSET_LSB,
ADC_RED_FINE_OFFSET_LSB,
ADC_BLUE_COARSE_OFFSET,
ADC_GREEN_COARSE_OFFSET,
ADC_RED_COARSE_OFFSET,
ADC_HSOUT_START,
ADC_LOOP_RESISTOR_CONTROL,
ADC_AUTO_LEVEL_CONTROL_NSH,
ADC_AUTO_LEVEL_CONTROL_NSV,
ADC_FINE_CLAMP_BLUE,
ADC_FINE_CLAMP_GREEN,
ADC_FINE_CLAMP_RED,
ADC_TRIM_CONTROL,
ADC_COARSE_CLAMP_CONTROL_LP,
ADC_COARSE_CLAMP_CONTROL_RED,
ADC_COARSE_CLAMP_CONTROL_GREEN,
ADC_COARSE_CLAMP_CONTROL_BLUE,
ADC_AUTO_LEVEL_CONTROL_ENABLE,
ADC_ALC_PLACEMENT,
ADC_SEEK_MODE_OVERRIDE,
ADC_OUTPUT_DIVIDER,
ADC_SETUP,
ADC_PIXEL_TOLERANCE,
ADC_TEST_OUTPUT,
ADC_PLL_POWER_DOWN,
ADC_PLL_START_UP_ENABLE,
ADC_MACROVISION_ENABLE,
ADC_VSYNC_ALIGNMENT,
ADC_FREE_RUN
}ADC_FunctionEnum;
/* These enumerated types define fields that may */
/* be assigned a limit range. New limit types may */
/* be added to the list but be sure to add them */
/* before ADC_NO_LIMITS. */
typedef enum ADC_FieldLimitsEnum
{
ADC_GAIN_LIMITS,
ADC_OFFSET_LIMITS,
ADC_PHASE_LIMITS,
ADC_PLL_LIMITS,
ADC_CLAMP_PLACEMENT_LIMITS,
ADC_CLAMP_DURATION_LIMITS,
ADC_HSYNC_PULSE_WIDTH_LIMITS,
ADC_SOG_SLICER_THRESHOLD_LIMITS,
ADC_SYNC_SEPARATOR_THRESHOLD_LIMITS,
ADC_PRE_COAST_LIMITS,
ADC_POST_COAST_LIMITS,
ADC_VCO_LIMITS,
ADC_CHARGE_PUMP_LIMITS,
ADC_BOOL_LIMITS,
ADC_INPUT_BANDWIDTH_LIMITS,
ADC_UPDATE_RATE_AUTO_OFFSET_LIMITS,
ADC_INPUT_MUX_LIMITS,
ADC_FINE_OFFSET_LSB_LIMITS,
ADC_COARSE_OFFSET_LIMITS,
ADC_LOOP_RESISTOR_CONTROL_LIMITS,
ADC_AUTO_LEVEL_CONTROL_NSH_LIMITS,
ADC_AUTO_LEVEL_CONTROL_NSV_LIMITS,
ADC_ADC_COARSE_CLAMP_CONTROL_LP_LIMITS,
ADC_NO_LIMITS
}ADC_FieldLimitsEnum;
/* This struct defines the entry for the field limits. */
/* The struct ADC_LimitStruct is defined in adc.h to */
/* to allow external access. */
typedef struct ADC_FieldLimitsStruct
{
ADC_FieldLimitsEnum LimitType;
ADC_LimitStruct Limits;
}ADC_FieldLimitsStruct;
typedef struct ADC_TableEntryStruct
{
ADC_FunctionEnum Function;
BOOL DoesExist;
uint08 BitPosition;
uint08 Mask;
uint08 Reg;
uint08 DefaultVal;
BOOL IsInverted;
ADC_FieldLimitsEnum LimitType;
}ADC_TableEntryStruct;
typedef struct
{
uint08 VCORange;
uint08 ChargePumpCurrent;
uint32 PixelFrequency;
}ADC_VCOAndChargePumpDataStruct;
#endif /* DOXYGEN_SHOULD_SKIP_THIS */
/*****************************************************************************/
/* Private constants ******************************************************/
/*****************************************************************************/
/*****************************************************************************/
/* The number of registers must be modified to match the device */
#define ADC_NUM_REGISTERS 0x31
#define ADC_HAS_48_BIT_PORT FALSE
#define ADC_HAS_LOOP_FILTER_CAPACITOR TRUE
/* Multi byte operations require knowledge of specific */
/* register addresses. These values go here. */
enum
{
ADC_PLL_DIVIDER_MSB_REG = 1,
ADC_BLUE_GAIN_REG = 8,
ADC_BLUE_OFFSET_REG = 11,
ADC_BLUE_COARSE_OFFSET_REG = 30
}ADC_ADCRegisterDefsEnum;
const ADC_FieldLimitsStruct ADC_FieldLimits[ADC_NO_LIMITS] =
{
/* Limit type Min Max */
ADC_GAIN_LIMITS, 0x0000, 0x00ff,
ADC_OFFSET_LIMITS, 0x0000, 0x00ff,
ADC_PHASE_LIMITS, 0x0000, 0x001f,
ADC_PLL_LIMITS, 0x012c, 0x0fff,
ADC_CLAMP_PLACEMENT_LIMITS, 0x0001, 0x00ff,
ADC_CLAMP_DURATION_LIMITS, 0x0001, 0x00ff,
ADC_HSYNC_PULSE_WIDTH_LIMITS, 0x0000, 0x00ff,
ADC_SOG_SLICER_THRESHOLD_LIMITS, 0x0000, 0x001f,
ADC_SYNC_SEPARATOR_THRESHOLD_LIMITS, 0x0000, 0x00ff,
ADC_PRE_COAST_LIMITS, 0x0000, 0x00ff,
ADC_POST_COAST_LIMITS, 0x0000, 0x00ff,
ADC_VCO_LIMITS, 0x0001, 0x0003,
ADC_CHARGE_PUMP_LIMITS, 0x0000, 0x0007,
ADC_BOOL_LIMITS, 0, 1,
ADC_INPUT_BANDWIDTH_LIMITS, 0x0000, 0x0003,
ADC_UPDATE_RATE_AUTO_OFFSET_LIMITS, 0x0000, 0x0002,
ADC_INPUT_MUX_LIMITS, 0x0000, 0x0003,
ADC_FINE_OFFSET_LSB_LIMITS, 0x0000, 0x0003,
ADC_COARSE_OFFSET_LIMITS, 0x0000, 0x003F,
ADC_LOOP_RESISTOR_CONTROL_LIMITS, 0x0000, 0x000F,
ADC_AUTO_LEVEL_CONTROL_NSH_LIMITS, 0x0000, 0x0007,
ADC_AUTO_LEVEL_CONTROL_NSV_LIMITS, 0x0000, 0x000F,
ADC_ADC_COARSE_CLAMP_CONTROL_LP_LIMITS, 0x0000, 0x0003
};
const ADC_TableEntryStruct ADC_FunctionTable[] =
{
/* B */
/* i */
/* t */
/* */
/* P */
/* o D */
/* E s e I L */
/* x i f n i */
/* i t M a v m */
/* s i a R u e i */
/* t o s e l r t */
/* Function s n k g t t s */
ADC_CHIP_REVISION, TRUE, 0, 0xFF, 0x00, 0, FALSE, ADC_NO_LIMITS,
/* Setting the PLL is a multi-byte operation. Its inclusion in this table is for */
/* the purpose of initialization. Therefore, no limits apply. */
ADC_PLL_MSB, TRUE, 0, 0xFF, 0x01, 0x54, FALSE, ADC_NO_LIMITS,
ADC_PLL_LSB, TRUE, 3, 0xF8, 0x02, 0x00, FALSE, ADC_NO_LIMITS,
ADC_VCO, TRUE, 6, 0xC0, 0x03, 0x01, FALSE, ADC_VCO_LIMITS,
ADC_CHARGE_PUMP, TRUE, 3, 0x38, 0x03, 0x03, FALSE, ADC_CHARGE_PUMP_LIMITS,
ADC_PHASE, TRUE, 3, 0xF8, 0x04, 0x03, FALSE, ADC_PHASE_LIMITS,
ADC_OUTPUT_DIVIDER, TRUE, 0, 0x01, 0x04, 0x00, FALSE, ADC_BOOL_LIMITS,
ADC_CLAMP_PLACEMENT, TRUE, 0, 0xFF, 0x05, 0x08, FALSE, ADC_CLAMP_PLACEMENT_LIMITS,
ADC_CLAMP_DURATION, TRUE, 0, 0xFF, 0x06, 0x10, FALSE, ADC_CLAMP_DURATION_LIMITS,
ADC_HSYNC_PULSEWIDTH, TRUE, 0, 0xFF, 0x07, 0x88, FALSE, ADC_HSYNC_PULSE_WIDTH_LIMITS,
ADC_RED_GAIN, TRUE, 0, 0xFF, 0x0A, 0x80, FALSE, ADC_GAIN_LIMITS,
ADC_GREEN_GAIN, TRUE, 0, 0xFF, 0x09, 0x80, FALSE, ADC_GAIN_LIMITS,
ADC_BLUE_GAIN, TRUE, 0, 0xFF, 0x08, 0x80, FALSE, ADC_GAIN_LIMITS,
ADC_RED_OFFSET, TRUE, 0, 0xFF, 0x0D, 0x80, FALSE, ADC_OFFSET_LIMITS,
ADC_GREEN_OFFSET, TRUE, 0, 0xFF, 0x0C, 0x80, FALSE, ADC_OFFSET_LIMITS,
ADC_BLUE_OFFSET, TRUE, 0, 0xFF, 0x0B, 0x80, FALSE, ADC_OFFSET_LIMITS,
ADC_HSYNC_IN_POLARITY_OVERRIDE, TRUE, 7, 0x80, 0x0E, ADC_MANUAL_SELECT_HSYNC_POLARITY, FALSE, ADC_BOOL_LIMITS,
ADC_HSYNC_INPUT_POLARITY, TRUE, 6, 0x40, 0x0E, ADC_HSYNC_IN_POSITIVE, FALSE, ADC_BOOL_LIMITS,
ADC_HSYNC_OUT_POLARITY, TRUE, 5, 0x20, 0x0E, ADC_HSYNC_OUT_POSITIVE, FALSE, ADC_BOOL_LIMITS,
ADC_ACTIVE_HSYNC_OVERRIDE, TRUE, 4, 0x10, 0x0E, ADC_MANUAL_HSYNC_SELECT, FALSE, ADC_BOOL_LIMITS,
ADC_ACTIVE_HSYNC_SELECT, TRUE, 3, 0x08, 0x0E, ADC_HSYNC_INPUT, FALSE, ADC_BOOL_LIMITS,
ADC_VSYNC_OUT_INVERT, TRUE, 2, 0x04, 0x0E, ADC_VSYNC_OUT_NOT_INVERTED, FALSE, ADC_BOOL_LIMITS,
ADC_ACTIVE_VSYNC_OVERRIDE, TRUE, 1, 0x02, 0x0E, ADC_MANUAL_VSYNC_SELECT, FALSE, ADC_BOOL_LIMITS,
ADC_ACTIVE_VSYNC_SELECT, TRUE, 0, 0x01, 0x0E, ADC_VSYNC_INPUT, FALSE, ADC_BOOL_LIMITS,
ADC_CLAMP_SOURCE, TRUE, 7, 0x80, 0x0F, ADC_INTERNAL_CLAMP, FALSE, ADC_BOOL_LIMITS,
ADC_CLAMP_POLARITY, TRUE, 6, 0x40, 0x0F, ADC_CLAMP_NEGATIVE, FALSE, ADC_BOOL_LIMITS,
ADC_COAST_SOURCE, TRUE, 5, 0x20, 0x0F, ADC_INTERNAL_COAST, FALSE, ADC_BOOL_LIMITS,
ADC_COAST_POLARITY_OVERRIDE, TRUE, 4, 0x10, 0x0F, ADC_AUTO_SELECT_COAST_POLARITY, FALSE, ADC_BOOL_LIMITS,
ADC_COAST_INPUT_POLARITY, TRUE, 3, 0x08, 0x0F, ADC_COAST_IN_POSITIVE, FALSE, ADC_BOOL_LIMITS,
ADC_SEEK_MODE_OVERRIDE, TRUE, 2, 0x04, 0x0F, 0x01, FALSE, ADC_BOOL_LIMITS,
ADC_CHIP_POWER, TRUE, 1, 0x02, 0x0F, ADC_CHIP_POWER_UP, FALSE, ADC_BOOL_LIMITS,
ADC_FREE_RUN, TRUE, 0, 0x01, 0x0F, 0x00, FALSE, ADC_BOOL_LIMITS,
ADC_SOG_SLICER_THRESHOLD, TRUE, 3, 0xF8, 0x10, 0x0C,/*0x10,*/ FALSE, ADC_SOG_SLICER_THRESHOLD_LIMITS,
ADC_RED_CLAMP_SELECT, TRUE, 0, 0x01, 0x10, ADC_CLAMP_TO_GROUND, FALSE, ADC_BOOL_LIMITS,
ADC_GREEN_CLAMP_SELECT, TRUE, 1, 0x02, 0x10, ADC_CLAMP_TO_GROUND, FALSE, ADC_BOOL_LIMITS,
ADC_BLUE_CLAMP_SELECT, TRUE, 2, 0x04, 0x10, ADC_CLAMP_TO_GROUND, FALSE, ADC_BOOL_LIMITS,
ADC_SYNC_SEPARATOR_THRESHOLD, TRUE, 0, 0xFF, 0x11, 0x47, FALSE, ADC_SYNC_SEPARATOR_THRESHOLD_LIMITS,
ADC_PRE_COAST, TRUE, 0, 0xFF, 0x12, 0x00, FALSE, ADC_PRE_COAST_LIMITS,
ADC_POST_COAST, TRUE, 0, 0xFF, 0x13, 0x00, FALSE, ADC_POST_COAST_LIMITS,
ADC_HSYNC_ACTIVITY_STATUS, TRUE, 7, 0x80, 0x14, 0x00, FALSE, ADC_BOOL_LIMITS,
ADC_ACTIVE_HSYNC_STATUS, TRUE, 6, 0x40, 0x14, 0x00, FALSE, ADC_BOOL_LIMITS,
ADC_HSYNC_IN_POLARITY_STATUS, TRUE, 5, 0x20, 0x14, 0x00, FALSE, ADC_BOOL_LIMITS,
ADC_VSYNC_ACTIVITY_STATUS, TRUE, 4, 0x10, 0x14, 0x00, FALSE, ADC_BOOL_LIMITS,
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