📄 1394.h
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/*++
Copyright (c) 1995 Microsoft Corporation
Module Name:
1394.h
Abstract:
Definitions for 1394 bus and/or port drivers
Author:
Shaun Pierce (shaunp) 5-Sep-95
Environment:
Kernel mode only
Revision History:
--*/
#ifndef _1394_H_
#define _1394_H_
#if (_MSC_VER >= 1020)
#pragma once
#endif
#ifdef __cplusplus
extern "C" {
#endif
//
// 1394 Node Address format
//
typedef struct _NODE_ADDRESS {
USHORT NA_Node_Number:6; // Bits 10-15
USHORT NA_Bus_Number:10; // Bits 0-9
} NODE_ADDRESS, *PNODE_ADDRESS;
//
// 1394 Address Offset format (48 bit addressing)
//
typedef struct _ADDRESS_OFFSET {
USHORT Off_High;
ULONG Off_Low;
} ADDRESS_OFFSET, *PADDRESS_OFFSET;
//
// 1394 I/O Address format
//
typedef struct _IO_ADDRESS {
NODE_ADDRESS IA_Destination_ID;
ADDRESS_OFFSET IA_Destination_Offset;
} IO_ADDRESS, *PIO_ADDRESS;
//
// 1394 Allocated Address Range format
//
typedef struct _ADDRESS_RANGE {
USHORT AR_Off_High;
USHORT AR_Length;
ULONG AR_Off_Low;
} ADDRESS_RANGE, *PADDRESS_RANGE;
//
// 1394 Self ID packet format
//
typedef struct _SELF_ID {
ULONG SID_Phys_ID:6; // Byte 0 - Bits 0-5
ULONG SID_Packet_ID:2; // Byte 0 - Bits 6-7
ULONG SID_Gap_Count:6; // Byte 1 - Bits 0-5
ULONG SID_Link_Active:1; // Byte 1 - Bit 6
ULONG SID_Zero:1; // Byte 1 - Bit 7
ULONG SID_Power_Class:3; // Byte 2 - Bits 0-2
ULONG SID_Contender:1; // Byte 2 - Bit 3
ULONG SID_Delay:2; // Byte 2 - Bits 4-5
ULONG SID_Speed:2; // Byte 2 - Bits 6-7
ULONG SID_More_Packets:1; // Byte 3 - Bit 0
ULONG SID_Initiated_Rst:1; // Byte 3 - Bit 1
ULONG SID_Port3:2; // Byte 3 - Bits 2-3
ULONG SID_Port2:2; // Byte 3 - Bits 4-5
ULONG SID_Port1:2; // Byte 3 - Bits 6-7
} SELF_ID, *PSELF_ID;
//
// Additional 1394 Self ID packet format (only used when More bit is on)
//
typedef struct _SELF_ID_MORE {
ULONG SID_Phys_ID:6; // Byte 0 - Bits 0-5
ULONG SID_Packet_ID:2; // Byte 0 - Bits 6-7
ULONG SID_PortA:2; // Byte 1 - Bits 0-1
ULONG SID_Reserved2:2; // Byte 1 - Bits 2-3
ULONG SID_Sequence:3; // Byte 1 - Bits 4-6
ULONG SID_One:1; // Byte 1 - Bit 7
ULONG SID_PortE:2; // Byte 2 - Bits 0-1
ULONG SID_PortD:2; // Byte 2 - Bits 2-3
ULONG SID_PortC:2; // Byte 2 - Bits 4-5
ULONG SID_PortB:2; // Byte 2 - Bits 6-7
ULONG SID_More_Packets:1; // Byte 3 - Bit 0
ULONG SID_Reserved3:1; // Byte 3 - Bit 1
ULONG SID_PortH:2; // Byte 3 - Bits 2-3
ULONG SID_PortG:2; // Byte 3 - Bits 4-5
ULONG SID_PortF:2; // Byte 3 - Bits 6-7
} SELF_ID_MORE, *PSELF_ID_MORE;
//
// 1394 Phy Configuration packet format
//
typedef struct _PHY_CONFIGURATION_PACKET {
ULONG PCP_Phys_ID:6; // Byte 0 - Bits 0-5
ULONG PCP_Packet_ID:2; // Byte 0 - Bits 6-7
ULONG PCP_Gap_Count:6; // Byte 1 - Bits 0-5
ULONG PCP_Set_Gap_Count:1; // Byte 1 - Bit 6
ULONG PCP_Force_Root:1; // Byte 1 - Bit 7
ULONG PCP_Reserved1:8; // Byte 2 - Bits 0-7
ULONG PCP_Reserved2:8; // Byte 3 - Bits 0-7
ULONG PCP_Inverse; // Inverse quadlet
} PHY_CONFIGURATION_PACKET, *PPHY_CONFIGURATION_PACKET;
//
// 1394 Asynchronous packet format
//
typedef struct _ASYNC_PACKET {
USHORT AP_Priority:4; // Bits 0-3 1st quadlet
USHORT AP_tCode:4; // Bits 4-7
USHORT AP_rt:2; // Bits 8-9
USHORT AP_tLabel:6; // Bits 10-15
NODE_ADDRESS AP_Destination_ID; // Bits 16-31
union { // 2nd quadlet
struct {
USHORT AP_Reserved:12; // Bits 0-11
USHORT AP_Rcode:4; // Bits 12-15
} Response;
USHORT AP_Offset_High; // Bits 0-15
} u;
NODE_ADDRESS AP_Source_ID; // Bits 16-31
ULONG AP_Offset_Low; // Bits 0-31 3rd quadlet
union { // 4th quadlet
struct {
USHORT AP_Extended_tCode; // Bits 0-15
USHORT AP_Data_Length; // Bits 16-31
} Block;
ULONG AP_Quadlet_Data; // Bits 0-31
} u1;
} ASYNC_PACKET, *PASYNC_PACKET;
//
// 1394 Isochronous packet header
//
typedef struct _ISOCH_HEADER {
ULONG IH_Sy:4; // Bits 0-3
ULONG IH_tCode:4; // Bits 4-7
ULONG IH_Channel:6; // Bits 8-13
ULONG IH_Tag:2; // Bits 14-15
ULONG IH_Data_Length:16; // Bits 16-31
} ISOCH_HEADER, *PISOCH_HEADER;
//
// 1394 Topology Map format
//
typedef struct _TOPOLOGY_MAP {
USHORT TOP_Length; // number of quadlets in map
USHORT TOP_CRC; // 16 bit CRC defined by 1212
ULONG TOP_Generation; // Generation number
USHORT TOP_Node_Count; // Node count
USHORT TOP_Self_ID_Count; // Number of Self IDs
SELF_ID TOP_Self_ID_Array[]; // Array of Self IDs
} TOPOLOGY_MAP, *PTOPOLOGY_MAP;
//
// 1394 Speed Map format
//
typedef struct _SPEED_MAP {
USHORT SPD_Length; // number of quadlets in map
USHORT SPD_CRC; // 16 bit CRC defined by 1212
ULONG SPD_Generation; // Generation number
UCHAR SPD_Speed_Code[4032];
} SPEED_MAP, *PSPEED_MAP;
//
// 1394 Config Rom format (always at 0xffff f0000400 : IEEE 1212)
//
typedef struct _CONFIG_ROM {
ULONG CR_Info; // 0x0
ULONG CR_Signiture; // 0x4 // bus info block
ULONG CR_BusInfoBlockCaps; // 0x8 // "
ULONG CR_Node_UniqueID[2]; // 0xC // "
ULONG CR_Root_Info; // 0x14
//
// the rest is the root directory which has variable definition and length
//
} CONFIG_ROM, *PCONFIG_ROM;
//
// 1394A Network channels register format
//
typedef struct _NETWORK_CHANNELS {
ULONG NC_Channel:6; // bits 0-5
ULONG NC_Reserved:18; // bits 6-23
ULONG NC_Npm_ID:6; // bits 24-29
ULONG NC_Valid:1; // bit 30
ULONG NC_One:1; // bit 31
} NETWORK_CHANNELSR, *PNETWORK_CHANNELS;
//
// 1394 Textual Leaf format
//
typedef struct _TEXTUAL_LEAF {
USHORT TL_CRC; // using 1994 CRC algorithm
USHORT TL_Length; // length of leaf in quads
ULONG TL_Spec_Id; // vendor defined
ULONG TL_Language_Id; // language Id
UCHAR TL_Data; // variable length data
} TEXTUAL_LEAF, *PTEXTUAL_LEAF;
//
// 1394 Cycle Time format
//
typedef struct _CYCLE_TIME {
ULONG CL_CycleOffset:12; // Bits 0-11
ULONG CL_CycleCount:13; // Bits 12-24
ULONG CL_SecondCount:7; // Bits 25-31
} CYCLE_TIME, *PCYCLE_TIME;
//
// Definition of an Address Mapping FIFO element
//
typedef struct _ADDRESS_FIFO {
SINGLE_LIST_ENTRY FifoList; // Singly linked list
PMDL FifoMdl; // Mdl for this FIFO element
} ADDRESS_FIFO, *PADDRESS_FIFO;
//
// Information block the bus driver passes to the higher device drivers
// when the notification handler is called
//
typedef struct _NOTIFICATION_INFO {
PMDL Mdl; // Supplied by device driver
ULONG ulOffset; // Where in buffer
ULONG nLength; // How big is the operation
ULONG fulNotificationOptions; // Which option occurred
PVOID Context; // Device driver supplied
PADDRESS_FIFO Fifo; // FIFO that completed
PVOID RequestPacket; // Pointer to request packet
PMDL ResponseMdl; // Pointer to response MDL
PVOID * ResponsePacket; // Pointer to pointer to response packet
PULONG ResponseLength; // Pointer to length of response
PKEVENT * ResponseEvent; // Event to be signaled
} NOTIFICATION_INFO, *PNOTIFICATION_INFO;
//
// Various definitions
//
#define IOCTL_1394_CLASS CTL_CODE( \
FILE_DEVICE_UNKNOWN, \
0x87, \
METHOD_IN_DIRECT, \
FILE_ANY_ACCESS \
)
//
// these guys are meant to be called from a ring 3 app
// call through the port device object
//
#define IOCTL_1394_TOGGLE_ENUM_TEST_ON CTL_CODE( \
FILE_DEVICE_UNKNOWN, \
0x88, \
METHOD_BUFFERED, \
FILE_ANY_ACCESS \
)
#define IOCTL_1394_TOGGLE_ENUM_TEST_OFF CTL_CODE( \
FILE_DEVICE_UNKNOWN, \
0x89, \
METHOD_BUFFERED, \
FILE_ANY_ACCESS \
)
//
// 1394 Additional NT DDK definitions
//
#define IRP_MN_BUS_RESET 0x87
#define RCODE ULONG
#define BASE_DEVICE_NAME L"\\Device\\1394BUS"
#define BASE_SYMBOLIC_LINK_NAME L"\\DosDevices\\1394BUS"
#define MAX_SUFFIX_SIZE 4*sizeof(WCHAR)
//
// 1394 ByteSwap definitions
//
#if defined(_X86_)
ULONG static __inline
bswap(ULONG value)
{
__asm mov eax, value
__asm bswap eax
}
#else
#define bswap(value) RtlUlongByteSwap(value)
#endif
#define bswapw(value) ( (((USHORT) (value)) & 0x00ff) << 8 | \
(((USHORT) (value)) & 0xff00) >> 8)
//
// 1394 Transaction codes
//
#define TCODE_WRITE_REQUEST_QUADLET 0 // 0000b
#define TCODE_WRITE_REQUEST_BLOCK 1 // 0001b
#define TCODE_WRITE_RESPONSE 2 // 0010b
#define TCODE_RESERVED1 3
#define TCODE_READ_REQUEST_QUADLET 4 // 0100b
#define TCODE_READ_REQUEST_BLOCK 5 // 0101b
#define TCODE_READ_RESPONSE_QUADLET 6 // 0110b
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