📄 2413addr.h
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#define rCISRCFMT (*(volatile unsigned *)0x4D800000) //Input Source Format
#define rCIWDOFST (*(volatile unsigned *)0x4D800004) //Window offset
#define rCIGCTRL (*(volatile unsigned *)0x4D800008) //Global control
#define rCIFCTRL1 (*(volatile unsigned *)0x4D80000C) //flash control 1
#define rCIFCTRL2 (*(volatile unsigned *)0x4D800010) //flash control 2
#define rCIDOWSFT2 (*(volatile unsigned *)0x4D800014) //Window option 2
#define rCICOYSA1 (*(volatile unsigned *)0x4D800018) //Y1 frame start address for codec DMA
#define rCICOYSA2 (*(volatile unsigned *)0x4D80001C) //Y2 frame start address for codec DMA
#define rCICOYSA3 (*(volatile unsigned *)0x4D800020) //Y3 frame start address for codec DMA
#define rCICOYSA4 (*(volatile unsigned *)0x4D800024) //Y4 frame start address for codec DMA
#define rCICOCBSA1 (*(volatile unsigned *)0x4D800028) //Cb1 frame start address for codec DMA
#define rCICOCBSA2 (*(volatile unsigned *)0x4D80002C) //Cb2 frame start address for codec DMA
#define rCICOCBSA3 (*(volatile unsigned *)0x4D800030) //Cb3 frame start address for codec DMA
#define rCICOCBSA4 (*(volatile unsigned *)0x4D800034) //Cb4 frame start address for codec DMA
#define rCICOCRSA1 (*(volatile unsigned *)0x4D800038) //Cr1 frame start address for codec DMA
#define rCICOCRSA2 (*(volatile unsigned *)0x4D80003C) //Cr2 frame start address for codec DMA
#define rCICOCRSA3 (*(volatile unsigned *)0x4D800040) //Cr3 frame start address for codec DMA
#define rCICOCRSA4 (*(volatile unsigned *)0x4D800044) //Cr4 frame start address for codec DMA
#define rCICOTRGFMT (*(volatile unsigned *)0x4D800048) //Target image format of codex DMA
#define rCICOCTRL (*(volatile unsigned *)0x4D80004C) //Codec DMA comtrol
#define rCICOSCPRERATIO (*(volatile unsigned *)0x4D800050) //Codec pre-scaler ratio control
#define rCICOSCPREDST (*(volatile unsigned *)0x4D800054) //Codec pre-scaler desitination format
#define rCICOSCCTRL (*(volatile unsigned *)0x4D800058) //Codec main-scaler control
#define rCICOTAREA (*(volatile unsigned *)0x4D80005C) //Codec pre-scaler desination format
#define rCICOSTATUS (*(volatile unsigned *)0x4D800064) //Codec path status
#define rCIIMGCPT (*(volatile unsigned *)0x4D8000A0) //Imahe capture enable command
#define rCICOCPTSEQ (*(volatile unsigned *)0x4D8000A4) //Codec dma capture sequence related
#define rCICOSCOS (*(volatile unsigned *)0x4D8000A8) //Codec scan line offset related
#define rCIIMGEFF (*(volatile unsigned *)0x4D8000B0) //Imahe Effects related
//ATA register base
#define ATA_BASE 0x4b800000
/*--------------------------------------------------------------*/
/* ATA Register */
/*--------------------------------------------------------------*/
#define ATA_CONTROL (ATA_BASE + 0x00) //ATA0 enable and clock down status
#define ATA_STATUS (ATA_BASE + 0x04) //ATA0 status
#define ATA_COMMAND (ATA_BASE + 0x08) //ATA0 command
#define ATA_SWRST (ATA_BASE + 0x0C) //ATA0 software reset
#define ATA_IRQ (ATA_BASE + 0x10) //ATA0 interrupt sources
#define ATA_IRQ_MASK (ATA_BASE + 0x14) //ATA0 interrupt mask
#define ATA_CFG (ATA_BASE + 0x18) //ATA0 configuration for ATA interface
#define ATA_PIO_TIME (ATA_BASE + 0x2C) //ATA0 PIO timing
#define ATA_UDMA_TIME (ATA_BASE + 0x30) //ATA0 UDMA timing
#define ATA_XFR_NUM (ATA_BASE + 0x34) //ATA0 transfer number
#define ATA_XFR_CNT (ATA_BASE + 0x38) //ATA0 current transfer count
#define ATA_TBUF_START (ATA_BASE + 0x3C) //ATA0 start address of track buffer
#define ATA_TBUF_SIZE (ATA_BASE + 0x40) //ATA0 size of track buffer
#define ATA_SBUF_START (ATA_BASE + 0x44) //ATA0 start address of Source buffer1
#define ATA_SBUF_SIZE (ATA_BASE + 0x48) //ATA0 size of source buffer1
#define ATA_CADR_TBUF (ATA_BASE + 0x4C) //ATA0 current write address of track buffer
#define ATA_CADR_SBUF (ATA_BASE + 0x50) //ATA0 current read address of source buffer
#define ATA_PIO_DTR (ATA_BASE + 0x54) //ATA0 PIO device data register
#define ATA_PIO_FED (ATA_BASE + 0x58) //ATA0 PIO device Feature/Error register
#define ATA_PIO_SCR (ATA_BASE + 0x5C) //ATA0 PIO sector count register
#define ATA_PIO_LLR (ATA_BASE + 0x60) //ATA0 PIO device LBA low register
#define ATA_PIO_LMR (ATA_BASE + 0x64) //ATA0 PIO device LBA middle register
#define ATA_PIO_LHR (ATA_BASE + 0x68) //ATA0 PIO device LBA high register
#define ATA_PIO_DVR (ATA_BASE + 0x6C) //ATA0 PIO device register
#define ATA_PIO_CSD (ATA_BASE + 0x70) //ATA0 PIO device command/status register
#define ATA_PIO_DAD (ATA_BASE + 0x74) //ATA0 PIO device control/alternate status register
#define ATA_PIO_READY (ATA_BASE + 0x78) //ATA0 PIO data read/write ready
#define ATA_PIO_RDATA (ATA_BASE + 0x7C) //ATA0 PIO read data from device data register
#define BUS_FIFO_STATUS (ATA_BASE + 0x90) //Internal AHBP fifo status
#define ATA_FIFO_STATUS (ATA_BASE + 0x94) //Internal ATA0 fifo status
/*=========================================================================
* ata Register Address
*=========================================================================
*/
#define DEV_ERROR (ATA_BASE + 0x58)
#define DEV_FEATURE (ATA_BASE + 0x58)
#define DEV_SECTOR (ATA_BASE + 0x5c)
#define DEV_LOWLBA (ATA_BASE + 0x60)
#define DEV_MIDLBA (ATA_BASE + 0x64)
#define DEV_HIGHLBA (ATA_BASE + 0x68)
#define DEV_DEVICE (ATA_BASE + 0x6c)
#define DEV_STATUS (ATA_BASE + 0x70)
#define DEV_COMMAND (ATA_BASE + 0x70)
#define DEV_ALTANATE (ATA_BASE + 0x74)
#define DEV_CONTROL (ATA_BASE + 0x74)
/*=========================================================================
* ata Command
*=========================================================================
*/
//#define IDENTIFYDEVICE 0xa1
#define IDENTIFYDEVICE 0xec
#define READSECTOR 0x20
#define READMULTIPLE 0xc4
#define READDMA 0xc8
#define WRITESECTOR 0x30
#define WRITEMULTIPLE 0xc5
#define WRITEDMA 0xca
#define SETFEATURES 0xEF
/*=========================================================================
* FIU interrupt
*=========================================================================
*/
#define ATAPI_MASK 0xffffffe0
//Exception vector
#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0))
#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4))
#define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8))
#define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xc))
#define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10))
#define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14))
#define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18))
#define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1c))
// Interrupt vector
#define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20))
#define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24))
#define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28))
#define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2c))
#define pISR_EINT4_7 (*(unsigned *)(_ISR_STARTADDRESS+0x30))
#define pISR_EINT8_23 (*(unsigned *)(_ISR_STARTADDRESS+0x34))
#define pISR_CAM (*(unsigned *)(_ISR_STARTADDRESS+0x38)) // Added for 2442.
#define pISR_BAT_FLT (*(unsigned *)(_ISR_STARTADDRESS+0x3c))
#define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40))
#define pISR_WDT (*(unsigned *)(_ISR_STARTADDRESS+0x44)) //Changed to pISR_WDT_AC97 for 2442A
#define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48))
#define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4c))
#define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50))
#define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54))
#define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58))
#define pISR_UART2 (*(unsigned *)(_ISR_STARTADDRESS+0x5c))
#define pISR_LCD (*(unsigned *)(_ISR_STARTADDRESS+0x60))
#define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64))
#define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68))
#define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6c))
#define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70))
#define pISR_SDI_CF (*(unsigned *)(_ISR_STARTADDRESS+0x74))
#define pISR_SPI0 (*(unsigned *)(_ISR_STARTADDRESS+0x78))
#define pISR_UART1 (*(unsigned *)(_ISR_STARTADDRESS+0x7c))
#define pISR_NFCON (*(unsigned *)(_ISR_STARTADDRESS+0x80)) // Added for 2442.
#define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84))
#define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88))
#define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8c))
#define pISR_UART0 (*(unsigned *)(_ISR_STARTADDRESS+0x90))
#define pISR_SPI1 (*(unsigned *)(_ISR_STARTADDRESS+0x94))
#define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98))
#define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0x9c))
// PENDING BIT
#define BIT_EINT0 (0x1)
#define BIT_EINT1 (0x1<<1)
#define BIT_EINT2 (0x1<<2)
#define BIT_EINT3 (0x1<<3)
#define BIT_EINT4_7 (0x1<<4)
#define BIT_EINT8_23 (0x1<<5)
#define BIT_CAM (0x1<<6)
#define BIT_BAT_FLT (0x1<<7)
#define BIT_TICK (0x1<<8)
#define BIT_WDT (0x1<<9)
#define BIT_TIMER0 (0x1<<10)
#define BIT_TIMER1 (0x1<<11)
#define BIT_TIMER2 (0x1<<12)
#define BIT_TIMER3 (0x1<<13)
#define BIT_TIMER4 (0x1<<14)
#define BIT_UART2 (0x1<<15)
#define BIT_LCD (0x1<<16)
#define BIT_DMA0 (0x1<<17)
#define BIT_DMA1 (0x1<<18)
#define BIT_DMA2 (0x1<<19)
#define BIT_DMA3 (0x1<<20)
#define BIT_SDI_CF (0x1<<21)
#define BIT_SPI0 (0x1<<22)
#define BIT_UART1 (0x1<<23)
#define BIT_NFCON (0x1<<24)
#define BIT_USBD (0x1<<25)
#define BIT_USBH (0x1<<26)
#define BIT_IIC (0x1<<27)
#define BIT_UART0 (0x1<<28)
#define BIT_SPI1 (0x1<<29)
#define BIT_RTC (0x1<<30)
#define BIT_ADC (0x1<<31)
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