2413_sdr.cmm

三星2413芯片的测试代码,对进行驱动开发很有帮助.

B:

; system controller initialization
 	res
 	sys.cpu arm926ej
 	sys.option enreset on
 	sys.option waitreset on
 	sys.o.ResBreak off
 	sys.JtagClock rtck
 	sys.Mode Up
 	;Break.delete /all
 
 	;r.s cpsr (r(cpsr)&0xffffff00)|0xd3

	d.s SD:0x53000000 %LE %LONG 0x0 ;disable watchdog

	d.s SD:0x48800004 %LE %LONG 0xc0 ;ebi


; 12MHz

	d.s SD:0x4C000014 %LE %LONG 0x65 ;set clkdiv, 1:2:4
;	d.s SD:0x4C000014 %LE %LONG 0x3 ;set clkdiv, 1:2:4

 	d.s SD:0x4C000004 %LE %LONG 0x0002a011 ;Mpll:200MHz, pll off(default=1[bit20])

	d.s SD:0x4C00001C %LE %LONG 0x00000030 ;//Clock source control Fout=mpll, Fout=upll


 	d.s SD:0x4C000008 %LE %LONG 0x0040070 ;Upll:96MHz



;SDRAM Initialization
; setting the configuration register rBANKCON123
; assert PALL
; wait refresh 255 cycle
; 2 auto-refresh cycle
; assert MRS
; normal refresh
; assert EMRS
; assert Normal mode
; now ready sdram operation

; 1st : configuration register
	d.s SD:0x48000000 %LE %LONG 0x48904 ; BANKCFG
	d.s SD:0x48000004 %LE %LONG 0x40 ; BANKCON1 - mobile dram controller
	d.s SD:0x48000008 %LE %LONG 0x57003a ; BANKCON2 - timing parameter
	d.s SD:0x4800000c %LE %LONG 0x80000030 ; BANKCON3 - EMRS register
	
;1st : issue precharge all command
 d.s SD:0x48000004 %LE %LONG 0x41
 
;2nd : make refresh cycle 32clk
 d.s SD:0x48000010 %LE %LONG 0xff
 
;3rd : wait 120clk
 r.s r0 r(r0)

;1st : issue MRS
 d.s SD:0x48000004 %LE %LONG 0x42

;4th : set normal operation refresh cycle
 d.s SD:0x48000010 %LE %LONG 0x313
 
;1st : issue EMRS
 d.s SD:0x48000004 %LE %LONG 0x43

;1st : issue Normal mode
 d.s SD:0x48000004 %LE %LONG 0x40



;d.load.elf C:\Temp\2413XTEST\Mcp_Project\2413xtest\Debug\2413xtest.axf
d.load.elf C:\work\2413\program\release\2413XTEST\Mcp_Project\2413xtest\Debug\2413xtest.axf

mmu.cid 0:0 4000

print "Setting is done"


enddo