isr_vectors.c

simulink real-time workshop for dragon12 development board from

/* System macros (EXT_MODE, etc.) -- generated by 'gen_cpp_req_defines_h.tlc' */
//#include <mc9s12dp256.h>		      /* debug only (UnimplementedISR) */
#include "cpp_req_defines.h"
#include "mc_timer.h"				    /* timer interrupt prototypes */

extern void near _Startup(void);       /* Startup routine */

/* interrupt service routines */
extern __interrupt void SCI0_RX_isr(void);           /* ext_svr_transport.c / mc_signal.c */
extern __interrupt void SCI1_RX_isr(void);           /* ext_svr_transport.c / mc_signal.c */
extern __interrupt void RadioServer_OnTick(void);    /* radioServer_timer.c */
extern __interrupt void RadioClient_OnTick(void);    /* radioClient_timer.c */


#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */
__interrupt void UnimplementedISR(void)
{
   /* Unimplemented ISRs trap.*/
   //DDRB = 0xff;	// debug
   //PORTB = 0xff;	// debug
   asm BGND;
}

typedef void (*near tIsrFunc)(void);
const tIsrFunc _vect[] @0xFF80 = {     /* Interrupt table */
        UnimplementedISR,                 /* vector 63 : (reserved) */
        UnimplementedISR,                 /* vector 62 : (reserved) */
        UnimplementedISR,                 /* vector 61 : (reserved) */
        UnimplementedISR,                 /* vector 60 : (reserved) */
        UnimplementedISR,                 /* vector 59 : (reserved) */
        UnimplementedISR,                 /* vector 58 : (reserved) */
        UnimplementedISR,                 /* vector 57 : PWM emergency shutdown */
        UnimplementedISR,                 /* vector 56 : PORT P */
        UnimplementedISR,                 /* vector 55 : MSCAN4 - transmit */
        UnimplementedISR,                 /* vector 54 : MSCAN4 - receive */
        UnimplementedISR,                 /* vector 53 : MSCAN4 - errors */
        UnimplementedISR,                 /* vector 52 : MSCAN4 - wakeup */
        UnimplementedISR,                 /* vector 51 : MSCAN3 - transmit */
        UnimplementedISR,                 /* vector 50 : MSCAN3 - receive */
        UnimplementedISR,                 /* vector 49 : MSCAN3 - errors */
        UnimplementedISR,                 /* vector 48 : MSCAN3 - wakeup */
        UnimplementedISR,                 /* vector 47 : MSCAN2 - transmit */
        UnimplementedISR,                 /* vector 46 : MSCAN2 - receive */
        UnimplementedISR,                 /* vector 45 : MSCAN2 - errors */
        UnimplementedISR,                 /* vector 44 : MSCAN2 - wakeup */
        UnimplementedISR,                 /* vector 43 : MSCAN1 - transmit */
        UnimplementedISR,                 /* vector 42 : MSCAN1 - receive */
        UnimplementedISR,                 /* vector 41 : MSCAN1 - errors */
        UnimplementedISR,                 /* vector 40 : MSCAN1 - wakeup */
        UnimplementedISR,                 /* vector 39 : MSCAN0 - transmit */
        UnimplementedISR,                 /* vector 38 : MSCAN0 - receive */
        UnimplementedISR,                 /* vector 37 : MSCAN0 - errors */
        UnimplementedISR,                 /* vector 36 : MSCAN0 - wakeup */
        UnimplementedISR,                 /* vector 35 : FLASH */
        UnimplementedISR,                 /* vector 34 : EEPROM */
        UnimplementedISR,                 /* vector 33 : SPI2 */
        UnimplementedISR,                 /* vector 32 : SPI1 */
        UnimplementedISR,                 /* vector 31 : IIC bus */
        UnimplementedISR,                 /* vector 30 : DLC */
        UnimplementedISR,                 /* vector 29 : SCME */
        UnimplementedISR,                 /* vector 28 : CRG lock */
        UnimplementedISR,                 /* vector 27 : Pulse accumulator B overflow */
        UnimplementedISR,                 /* vector 26 : Modulus down counter underflow */
        UnimplementedISR,                 /* vector 25 : PORT H */
        UnimplementedISR,                 /* vector 24 : PORT J */
        UnimplementedISR,                 /* vector 23 : ATD1 */
        UnimplementedISR,                 /* vector 22 : ATD0 */
	#if SCI1_COMMS > 0
        SCI1_RX_isr,                      /* vector 21 : SCI1 (TIE, TCIE, RIE, ILIE) */
    #else
        UnimplementedISR,                 /* vector 21 : SCI1 (TIE, TCIE, RIE, ILIE) */
    #endif
	#if SCI0_COMMS > 0
        SCI0_RX_isr,                      /* vector 20 : SCI0 (TIE, TCIE, RIE, ILIE) */
    #else
        UnimplementedISR,                 /* vector 20 : SCI0 (TIE, TCIE, RIE, ILIE) */
    #endif
        UnimplementedISR,                 /* vector 19 : SPI0 */
        UnimplementedISR,                 /* vector 18 : Pulse accumulator input edge */
        UnimplementedISR,                 /* vector 17 : Pulse accumulator A overflow */
        #if (HAS_TIMERBLOCKS > 0) | (HAS_RFCOMMS > 0)
          TOF_ISR,                        /* vector 16 : (TOF, timer overflow interrupt) */
        #else
          UnimplementedISR,               /* vector 16 : (TOF, timer overflow interrupt) */
        #endif
    #if CORE_TIMER == CORE_T7ISR
        isr_timer7,                       /* vector 15 : Timer channel 7 (mc_main) */
    #else
      #if T7_MODE > 0
        T7_ISR,                           /* vector 15 : (C7I, timer interrupt channel 7)  */
      #else
        UnimplementedISR,                 /* vector 15 : (C7I, timer interrupt channel 7)  */
      #endif
    #endif
    #if T6_MODE > 0
      T6_ISR,		                          /* vector 14 : (C6I, timer interrupt channel 6)  */
    #else
      UnimplementedISR,                   /* vector 14 : (C6I, timer interrupt channel 6)  */
    #endif
    #if T5_MODE > 0
      T5_ISR,		                          /* vector 13 : (C5I, timer interrupt channel 5)  */
    #else
      UnimplementedISR,                   /* vector 13 : (C5I, timer interrupt channel 5)  */
    #endif
    #if T4_MODE > 0
      T4_ISR,		                          /* vector 12 : (C4I, timer interrupt channel 4)  */
    #else
      UnimplementedISR,                   /* vector 12 : (C4I, timer interrupt channel 4)  */
    #endif
    #if T3_MODE > 0
      T3_ISR,		                          /* vector 11 : (C3I, timer interrupt channel 3)  */
    #else
      UnimplementedISR,                   /* vector 11 : (C3I, timer interrupt channel 3)  */
    #endif
    #if T2_MODE > 0
      T2_ISR,		                          /* vector 10 : (C2I, timer interrupt channel 2)  */
    #else
      UnimplementedISR,                   /* vector 10 : (C2I, timer interrupt channel 2)  */
    #endif
    #if T1_MODE > 0
      T1_ISR,		                          /* vector 09 : (C1I, timer interrupt channel 1)  */
    #else
      UnimplementedISR,                   /* vector 09 : (C1I, timer interrupt channel 1)  */
    #endif
    #if T0_MODE > 0
      T0_ISR,		                          /* vector 08 : (C0I, timer interrupt channel 0)  */
    #else
        #if HAS_RFCOMMS == 1
          RadioServer_OnTick,             /* vector 08 : (C0I, timer interrupt channel 0)  */
        #else
			#if HAS_RFCOMMS == 2
				RadioClient_OnTick,       /* vector 08 : (C0I, timer interrupt channel 0)  */
			#else
				UnimplementedISR,         /* vector 08 : (C0I, timer interrupt channel 0)  */
			#endif
		#endif
    #endif
    #if CORE_TIMER == CORE_RTI
        RTI_isr,		                      /* vector 07 : Real-Time Interrupt (RTI) */
    #else
        UnimplementedISR,                 /* vector 07 : Real-Time Interrupt (RTI) */
    #endif
        UnimplementedISR,                 /* vector 06 : IRQ */
        UnimplementedISR,                 /* vector 05 : XIRQ */
        UnimplementedISR,                 /* vector 04 : SWI */
        UnimplementedISR,                 /* vector 03 : Unimplemented Instruction trap */
        UnimplementedISR,                 /* vector 02 : COP failure reset*/
        UnimplementedISR,                 /* vector 01 : Clock monitor fail reset */
        _Startup                          /* vector 00 : Reset vector */
   };