startup_virtex2.v

来自「xilinx公司的开放的源码」· Verilog 代码 · 共 26 行

// $Header: /home/oc/cvs/or1k/xess/xsv_fpga/orp_soc/lib/xilinx/unisims/STARTUP_VIRTEX2.v,v 1.1 2002/03/28 20:15:31 lampret Exp $
/*

FUNCTION	: Special Function Cell, STARTUP_VIRTEX2

*/

`timescale  100 ps / 10 ps

`celldefine

module STARTUP_VIRTEX2 (CLK, GSR, GTS);

    parameter cds_action = "ignore";

    input  CLK, GSR, GTS;

    tri0 GSR, GTS;

	assign glbl.GSR = GSR;
	assign glbl.GTS = GTS;

endmodule

`endcelldefine