dcm.v

xilinx公司的开放的源码

    clk1x_5050 <= 0;
    clk1x_shift125 <= 0;
    clk1x_shift250 <= 0;
    CLK270 <= 0;
    CLK2X <= 0;
    CLK2X180 <= 0;
    clk2x_shift <= 0;
    CLK90 <= 0;
    CLKDV <= 0;
    clkfb_window <= 0;
    CLKFX <= 0;
    CLKFX180 <= 0;
    clkfx_int <= 0;
    clkin_5050 <= 0;
    clkin_edge[0] <= 1'bx;
    clkin_edge[1] <= 1'bx;
    clkin_window <= 0;
    clklost_out <= 0;
    count11 <= 0;
    count13 <= 0;
    count15 <= 0;
    count3 <= 0;
    count4 <= 0;
    count5 <= 0;
    count7 <= 0;
    count9 <= 0;
    delay <= 0;
    delay_fb <= 0;
    delay_found <= 0;
    divider <= 0;
    generate <= 0;
    lock_clkfb <= 0;
    lock_clkin <= 0;
    lock_delay <= 0;
    lock_period <= 0;
    locked_out <= 0;
    psdone_out <= 0;
    pslock <= 0;
    psoverflow_out <= 0;
    case (CLKOUT_PHASE_SHIFT)
      "NONE"     : ps_in <= 0;
      "none"     : ps_in <= 0;
      "FIXED"   : ps_in <= PHASE_SHIFT + 256;
      "fixed"   : ps_in <= PHASE_SHIFT + 256;
      "VARIABLE" : ps_in <= PHASE_SHIFT + 256;
      "variable" : ps_in <= PHASE_SHIFT + 256;
    endcase
  end
end

always @ (posedge clkfb_in) begin
  #0   clkfb_window = 1;
  #100 clkfb_window = 0;
end

always @ (posedge clkin_in) begin
  #0   clkin_window = 1;
  #100 clkin_window = 0;
end

always @ (posedge clkin_in) begin
  #1
  if (clkfb_window && delay_found)
    lock_clkin <= 1;
  else
    lock_clkin <= 0;
end

always @ (posedge clkfb_in) begin
  #1
  if (clkin_window && delay_found)
    lock_clkfb <= 1;
  else
    lock_clkfb <= 0;
  @ (posedge clkfb_in);
end

always @ (lock_clkin or lock_clkfb) begin
  if (lock_clkin || lock_clkfb)
    lock_delay <= 1;
  else
    lock_delay <= 0;
end

//
// generate master reset signal
//
always @ (posedge clkin_in) begin
   {rst_2,rst_1} <= {rst_1,rst_in};
end

//
// generate lock signal
//
always @ (posedge clkin_in) begin
  if ((clkfb_type == 0) & lock_period)
    locked_out <= 1;
  else
    locked_out <= lock_delay & lock_period & ~rst_2;
end

//
// generate the clk0_int
//
always @ (clkin_in) begin
  if (delay_found)
    clk1x <= #delay_fb clkin_in;
end

always @ (posedge clkin_in) begin
    clkin_5050 <= 1;
    #(period/2)
    clkin_5050 <= 0;
end

always @ (clkin_5050) begin
  if (delay_found)
    clk1x_5050 <= #delay_fb clkin_5050;
end

assign clk0_int = (clk1x_type) ? clk1x_5050 : clk1x;

//
// generate the clk2x_int
//
always @(clk1x_5050) begin
  clk1x_shift125 <= #(period/8) clk1x_5050;
  clk1x_shift250 <= #(period/4) clk1x_5050;
end

assign clk2x_2575 = clk1x_5050 & ~clk1x_shift250;
assign clk2x_5050 = clk1x_5050 ^ clk1x_shift250;

always @(clk2x_5050 or clk2x_2575) begin
  if (locked_out)
    clk2x_int = clk2x_5050;
  else
    clk2x_int = clk2x_2575;
end

//
// generate the clk4x_int
//
always @(clk2x_5050) begin
  clk2x_shift <= #(period/8) clk2x_5050;
end

assign clk4x_int = clk2x_5050 ^ clk2x_shift;

//
// generate the clkdv_int
//

always @(posedge clk4x_int) begin
  if (dll_mode_type) begin
    if (count3 == 0)
      divider[3] <= 1;
    if (count3 == 2)
      divider[3] <= 0;
  end
  else
    if (count3 == 0 || count3 == 3)
      divider[3] <= divider[3] + 1;
  count3 <= (count3 + 1) % 6;
end

always @(posedge clk4x_int) begin
  if (count4 == 0)
    divider[4] <= divider[4] + 1;
  count4 <= (count4 + 1) % 4;
end

always @(posedge clk4x_int) begin
  if (dll_mode_type) begin
    if (count5 == 0)
      divider[5] <= 1;
    if (count5 == 4)
      divider[5] <= 0;
  end
  else
    if (count5 == 0 || count5 == 5)
      divider[5] <= divider[5] + 1;
  count5 <= (count5 + 1) % 10;
end

always @(posedge divider[3]) begin
  divider[6] <= divider[6] + 1;
end

always @(posedge clk4x_int) begin
  if (dll_mode_type) begin
    if (count7 == 0)
      divider[7] <= 1;
    if (count7 == 6)
      divider[7] <= 0;
  end
  else
    if (count7 == 0 || count7 == 7)
      divider[7] <= divider[7] + 1;
  count7 <= (count7 + 1) % 14;
end

always @(posedge divider[4]) begin
  divider[8] <= divider[8] + 1;
end

always @(posedge clk4x_int) begin
  if (dll_mode_type) begin
    if (count9 == 0)
      divider[9] <= 1;
    if (count9 == 8)
      divider[9] <= 0;
  end
  else
    if (count9 == 0 || count9 == 9)
      divider[9] <= divider[9] + 1;
  count9 <= (count9 + 1) % 18;
end

always @(posedge divider[5]) begin
  divider[10] <= divider[10] + 1;
end

always @(posedge clk4x_int) begin
  if (dll_mode_type) begin
    if (count11 == 0)
      divider[11] <= 1;
    if (count11 == 10)
      divider[11] <= 0;
  end
  else
    if (count11 == 0 || count11 == 11)
      divider[11] <= divider[11] + 1;
  count11 <= (count11 + 1) % 22;
end

always @(posedge divider[6]) begin
  divider[12] <= divider[12] + 1;
end

always @(posedge clk4x_int) begin
  if (dll_mode_type) begin
    if (count13 == 0)
      divider[13] <= 1;
    if (count13 == 12)
      divider[13] <= 0;
  end
  else
    if (count13 == 0 || count13 == 13)
      divider[13] <= divider[13] + 1;
  count13 <= (count13 + 1) % 26;
end

always @(posedge divider[7]) begin
  divider[14] <= divider[14] + 1;
end

always @(posedge clk4x_int) begin
  if (dll_mode_type) begin
    if (count15 == 0)
      divider[15] <= 1;
    if (count15 == 14)
      divider[15] <= 0;
  end
  else
    if (count15 == 0 || count15 == 15)
      divider[15] <= divider[15] + 1;
  count15 <= (count15 + 1) % 30;
end

always @(posedge divider[8]) begin
  divider[16] <= divider[16] + 1;
end

always @(posedge divider[9]) begin
  divider[18] <= divider[18] + 1;
end

always @(posedge divider[10]) begin
  divider[20] <= divider[20] + 1;
end

always @(posedge divider[11]) begin
  divider[22] <= divider[22] + 1;
end

always @(posedge divider[12]) begin
  divider[24] <= divider[24] + 1;
end

always @(posedge divider[13]) begin
  divider[26] <= divider[26] + 1;
end

always @(posedge divider[14]) begin
  divider[28] <= divider[28] + 1;
end

always @(posedge divider[15]) begin
  divider[30] <= divider[30] + 1;
end

always @(posedge divider[16]) begin
  divider[32] <= divider[32] + 1;
end

assign clkdv_int = divider[divide_type];

//
// generate fx output signal
//

always @(locked_out) begin
  if (locked_out) begin
    period_fx = period * denominator / numerator;
    while (period > 0) begin
      generate = !generate;
      for (n = 1; n <= denominator; n = n + 1) begin
        #(period);
      end
    end
  end
end

always @(generate) begin
  if (period_fx > 0) begin
    for (d = 1; d < numerator; d = d + 1) begin
      clkfx_int <= 1;
      #(period_fx/2);
      clkfx_int <= 0;
      #(period_fx/2);
    end
    clkfx_int <= 1;
    #(period_fx/2);
    clkfx_int <= 0;
  end
end

//
// generate all output signal
//
always @ (clk0_int) begin
    CLK0 <= clk0_int;
end

always @ (clk0_int) begin
    CLK90 <= #(period/4) clk0_int;
end

always @ (clk0_int) begin
    CLK180 <= #(period/2) clk0_int;
end

always @ (clk0_int) begin
    CLK270 <= #(3*period/4) clk0_int;
end

always @ (clk2x_int) begin
    CLK2X <= clk2x_int;
end

always @ (clk2x_int) begin
    CLK2X180 <= #(period/4) clk2x_int;
end

always @ (clkdv_int) begin
  if (locked_out)
    CLKDV <= #(period) clkdv_int;
end

always @ (clkfx_int) begin
    CLKFX <= #(delay_fb) clkfx_int;
end

always @ (clkfx_int) begin
    CLKFX180 <= #(delay_fb + period_fx/2) clkfx_int;
end

specify
	specparam CLKFBDLYLH = 0:0:0, CLKFBDLYHL = 0:0:0;
	specparam CLKINDLYLH = 0:0:0, CLKINDLYHL = 0:0:0;
	specparam DSSENDLYLH = 0:0:0, DSSENDLYHL = 0:0:0;
	specparam PSCLKDLYLH = 0:0:0, PSCLKDLYHL = 0:0:0;
	specparam PSENDLYLH = 0:0:0, PSENDLYHL = 0:0:0;
	specparam PSINCDECDLYLH = 0:0:0, PSINCDECDLYHL = 0:0:0;
	specparam RSTDLYLH = 0:0:0, RSTDLYHL = 0:0:0;
	specparam LOCKEDDLYLH = 0:0:0, LOCKEDDLYHL = 0:0:0;
	specparam PSDONEDLYLH = 0:0:0, PSDONEDLYHL = 0:0:0;
	specparam STATUS0DLYLH = 0:0:0, STATUS0DLYHL = 0:0:0;
	specparam STATUS1DLYLH = 0:0:0, STATUS1DLYHL = 0:0:0;
	specparam STATUS2DLYLH = 0:0:0, STATUS2DLYHL = 0:0:0;
	specparam STATUS3DLYLH = 0:0:0, STATUS3DLYHL = 0:0:0;
	specparam STATUS4DLYLH = 0:0:0, STATUS4DLYHL = 0:0:0;
	specparam STATUS5DLYLH = 0:0:0, STATUS5DLYHL = 0:0:0;
	specparam STATUS6DLYLH = 0:0:0, STATUS6DLYHL = 0:0:0;
	specparam STATUS7DLYLH = 0:0:0, STATUS7DLYHL = 0:0:0;

	specparam PWCLKINHI = 0:0:0, PWCLKINLO = 0:0:0;
	specparam PWPSCLKHI = 0:0:0, PWPSCLKLO = 0:0:0;
	specparam PWRSTHI = 0:0:0;
	specparam MINPERCLKIN = 10:10:10;
	specparam MINPERPSCLK = 10:10:10;

	specparam SUPSENHIPSCLK = 0:0:0, SUPSENLOPSCLK = 0:0:0;
	specparam HOLDPSENHIPSCLK = 0:0:0, HOLDPSENLOPSCLK = 0:0:0;
	specparam SUPSINCDECHIPSCLK = 0:0:0, SUPSINCDECLOPSCLK = 0:0:0;
	specparam HOLDPSINCDECHIPSCLK = 0:0:0, HOLDPSINCDECLOPSCLK = 0:0:0;

	(CLKIN => LOCKED) = (CLKINDLYLH + LOCKEDDLYLH, CLKINDLYHL + LOCKEDDLYHL);

	$setup (posedge PSEN, posedge PSCLK, SUPSENHIPSCLK, notifier);
	$setup (negedge PSEN, posedge PSCLK, SUPSENLOPSCLK, notifier);
	$hold (posedge PSCLK, posedge PSEN, HOLDPSENHIPSCLK, notifier);
	$hold (posedge PSCLK, negedge PSEN, HOLDPSENLOPSCLK, notifier);
	$setup (posedge PSINCDEC, posedge PSCLK, SUPSINCDECHIPSCLK, notifier);
	$setup (negedge PSINCDEC, posedge PSCLK, SUPSINCDECLOPSCLK, notifier);
	$hold (posedge PSCLK, posedge PSINCDEC, HOLDPSINCDECHIPSCLK, notifier);
	$hold (posedge PSCLK, negedge PSINCDEC, HOLDPSINCDECLOPSCLK, notifier);

	$period (posedge CLKIN, MINPERCLKIN, notifier);
	$period (posedge PSCLK, MINPERCLKIN, notifier);
	$width (posedge CLKIN, PWCLKINHI, 0, notifier);
	$width (negedge CLKIN, PWCLKINLO, 0, notifier);
	$width (posedge PSCLK, PWPSCLKHI, 0, notifier);
	$width (negedge PSCLK, PWPSCLKLO, 0, notifier);
	$width (posedge RST, PWRSTHI, 0, notifier);
endspecify

endmodule