and4.v

xilinx公司的开放的源码

// $Header: /home/oc/cvs/or1k/xess/xsv_fpga/orp_soc/lib/xilinx/unisims/AND4.v,v 1.1 2002/03/28 20:15:25 lampret Exp $

/*

FUNCTION	: 4-INPUT AND GATE

*/

`timescale  100 ps / 10 ps

`celldefine

module AND4 (O, I0, I1, I2, I3);

    parameter cds_action = "ignore";

    output O;

    input  I0, I1, I2, I3;

    and A1 (O, I0, I1, I2, I3);

    specify
	(I0 *> O) = (1, 1);
	(I1 *> O) = (1, 1);
	(I2 *> O) = (1, 1);
	(I3 *> O) = (1, 1);
    endspecify

endmodule

`endcelldefine