and12.v

来自「xilinx公司的开放的源码」· Verilog 代码 · 共 41 行

// $Header: /home/oc/cvs/or1k/xess/xsv_fpga/orp_soc/lib/xilinx/unisims/AND12.v,v 1.1 2002/03/28 20:15:25 lampret Exp $

/*

FUNCTION	: 12-INPUT AND GATE

*/

`timescale  100 ps / 10 ps

`celldefine

module AND12 (O, I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11);

    parameter cds_action = "ignore";

    output O;

    input  I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11;

    and O1 (O, I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11);

    specify
	(I0 *> O) = (1, 1);
	(I1 *> O) = (1, 1);
	(I2 *> O) = (1, 1);
	(I3 *> O) = (1, 1);
	(I4 *> O) = (1, 1);
	(I5 *> O) = (1, 1);
	(I6 *> O) = (1, 1);
	(I7 *> O) = (1, 1);
	(I8 *> O) = (1, 1);
	(I9 *> O) = (1, 1);
	(I10 *> O) = (1, 1);
	(I11 *> O) = (1, 1);
    endspecify

endmodule

`endcelldefine