example3.rul

Source code: Embedded software for ARM processor development: MMU table generation source code.

BASE_ADDRESS    0x00004000      /* table generated to this base address */

/* In this rule set, 3MBytes of contiguous RAM is mapped
   down to 0x00000000. This removes the need for a dedicated 1Mbyte section of RAM
   to hold the shadow copy of the FLASH code image, allowing more efficient use of
   the available RAM.
*/

/* MMU Level 1 Table generation data */

LEVEL 1

/* Virtual space */                     
/* 1MB FLASH mapped to RAM */ VIRTUAL 0x00000000 TO 0x000FFFFF PHYSICAL 0xC0400000  PAGES
/* Contiguous RAM 2nd MB   */ VIRTUAL 0x00100000 TO 0x001FFFFF PHYSICAL 0xC1000000  PAGES 
/* Contiguous RAM 3rd MB   */ VIRTUAL 0x00200000 TO 0x002FFFFF PHYSICAL 0xC1400000  PAGES 
/* Gap to 0x04000000       */ VIRTUAL 0x00300000 TO 0x03FFFFFF PHYSICAL 0x00300000  FAULT 
/* uncached copy 2MB FLASH */ VIRTUAL 0x04000000 TO 0x041FFFFF PHYSICAL 0x00000000  SECTION  FULL_ACCESS  NOT CACHEABLE AND NOT BUFFERABLE 
/* Gap to 0x07000000       */ VIRTUAL 0x04200000 TO 0x06FFFFFF PHYSICAL 0x04200000  FAULT 
/* 1MB FLASH Disk                  */ VIRTUAL 0x07000000 TO 0x070FFFFF PHYSICAL 0x00100000  SECTION  FULL_ACCESS  CACHEABLE AND NOT BUFFERABLE 
/* Gap to 0x0C000000       */ VIRTUAL 0x07100000 TO 0x0BFFFFFF PHYSICAL 0x08200000  FAULT 
/* Video RAM                       */ VIRTUAL 0x0C000000 TO 0x0C0FFFFF PHYSICAL 0xC0000000  PAGES 
/* Gap to 0x0D000000       */ VIRTUAL 0x0C100000 TO 0x0CFFFFFF PHYSICAL 0x0C100000  FAULT 
/* RAM disk                                */ VIRTUAL 0x0D000000 TO 0x0D0FFFFF PHYSICAL 0xC0010000  PAGES 
/* Expansion area          */ VIRTUAL 0x0D100000 TO 0x501FFFFF PHYSICAL 0x0D100000  SECTION  FULL_ACCESS  NOT CACHEABLE AND NOT BUFFERABLE 
/* External hardware       */ VIRTUAL 0x50200000 TO 0x503FFFFF PHYSICAL 0x50200000  SECTION  FULL_ACCESS  NOT CACHEABLE AND NOT BUFFERABLE 
/* Gap to 0x60000000       */ VIRTUAL 0x50400000 TO 0x5FFFFFFF PHYSICAL 0x50400000  FAULT 
/* SRAM                                    */ VIRTUAL 0x60000000 TO 0x600FFFFF PHYSICAL 0x60000000  SECTION  FULL_ACCESS  CACHEABLE AND BUFFERABLE 
/* Gap to 0x80000000       */ VIRTUAL 0x60100000 TO 0x7FFFFFFF PHYSICAL 0x60100000  FAULT 
/* Hardware registers      */ VIRTUAL 0x80000000 TO 0x800FFFFF PHYSICAL 0x80000000  PAGES 
/* Gap to 0xC0000000       */ VIRTUAL 0x80100000 TO 0xBFFFFFFF PHYSICAL 0x80100000  FAULT 
/* Non-contiguous RAM      */ VIRTUAL 0xC0000000 TO 0xCFFFFFFF PHYSICAL 0xC0000000  SECTION  FULL_ACCESS  CACHEABLE AND NOT BUFFERABLE 
/* Remaining space unused  */ VIRTUAL 0xD0000000 TO 0xFFFFFFFF PHYSICAL 0xD0000000  FAULT 


/* Each section of level2 data shown below maps 1MB of virtual space.
   NOTE:: IT IS VERY IMPORTANT THAT THE ENTRIES SHOWN BELOW ARE IN THE ORDER
          THEY ARE REFERENCED IN THE LEVEL 1 DATA (above)
*/

/* MMU Level 2 Table generation data */

LEVEL 2

/* FLASH shadow image   */ VIRTUAL 0x00000000 TO 0x0007FFFF PHYSICAL 0xC0400000  LARGEPAGES  FULL_ACCESS      CACHEABLE AND BUFFERABLE 
/* FLASH shadow image   */ VIRTUAL 0x00080000 TO 0x000FFFFF PHYSICAL 0xC0500000  LARGEPAGES  FULL_ACCESS      CACHEABLE AND BUFFERABLE 

/* Contiguous RAM 2nd MB*/ VIRTUAL 0x00100000 TO 0x0017FFFF PHYSICAL 0xC1000000  LARGEPAGES  FULL_ACCESS      CACHEABLE AND BUFFERABLE 
/* Contiguous RAM 2nd MB*/ VIRTUAL 0x00180000 TO 0x001FFFFF PHYSICAL 0xC1100000  LARGEPAGES  FULL_ACCESS      CACHEABLE AND BUFFERABLE 

/* Contiguous RAM 3rd MB*/ VIRTUAL 0x00200000 TO 0x0027FFFF PHYSICAL 0xC1400000  LARGEPAGES  FULL_ACCESS      CACHEABLE AND BUFFERABLE 
/* Contiguous RAM 3rd MB*/ VIRTUAL 0x00280000 TO 0x002FFFFF PHYSICAL 0xC1500000  LARGEPAGES  FULL_ACCESS      CACHEABLE AND BUFFERABLE 

/* Video RAM RAM bank0  */ VIRTUAL 0x0C000000 TO 0x0C00FFFF PHYSICAL 0xC0000000  LARGEPAGES  FULL_ACCESS      CACHEABLE AND BUFFERABLE 
/*+privilege mode stacks*/ VIRTUAL 0x0C010000 TO 0x0C0FFFFF PHYSICAL 0x0C010000  LARGEPAGES  NO_ACCESS    NOT CACHEABLE AND NOT BUFFERABLE 

/* RAM disk - RAM bank0 */ VIRTUAL 0x0D000000 TO 0x0D06FFFF PHYSICAL 0xC0010000  LARGEPAGES  FULL_ACCESS      CACHEABLE AND BUFFERABLE 
/* RAM disk - RAM bank1 */ VIRTUAL 0x0D070000 TO 0x0D0EFFFF PHYSICAL 0xC0100000  LARGEPAGES  FULL_ACCESS      CACHEABLE AND BUFFERABLE 
/* RAM disk - no RAM    */ VIRTUAL 0x0D0F0000 TO 0x0D0FFFFF PHYSICAL 0x0D0F0000  LARGEPAGES  NO_ACCESS    NOT CACHEABLE AND NOT BUFFERABLE 

/* Hardware Registers   */ VIRTUAL 0x80000000 TO 0x80001FFF PHYSICAL 0x80000000  SMALLPAGES  FULL_ACCESS  NOT CACHEABLE AND NOT BUFFERABLE 
/* Hardware Registers   */ VIRTUAL 0x80002000 TO 0x80003FFF PHYSICAL 0x80002000  SMALLPAGES  NO_ACCESS    NOT CACHEABLE AND NOT BUFFERABLE 
/* Hardware Registers   */ VIRTUAL 0x80004000 TO 0x80005FFF PHYSICAL 0x80004000  SMALLPAGES  FULL_ACCESS  NOT CACHEABLE AND NOT BUFFERABLE 
/* Hardware Registers   */ VIRTUAL 0x80006000 TO 0x80007FFF PHYSICAL 0x80006000  SMALLPAGES  NO_ACCESS    NOT CACHEABLE AND NOT BUFFERABLE 
/* Hardware Registers   */ VIRTUAL 0x80008000 TO 0x80009FFF PHYSICAL 0x80008000  SMALLPAGES  FULL_ACCESS  NOT CACHEABLE AND NOT BUFFERABLE 
/* Hardware Registers   */ VIRTUAL 0x8000A000 TO 0x8000BFFF PHYSICAL 0x8000A000  SMALLPAGES  NO_ACCESS    NOT CACHEABLE AND NOT BUFFERABLE 
/* Hardware Registers   */ VIRTUAL 0x8000C000 TO 0x8000DFFF PHYSICAL 0x8000C000  SMALLPAGES  FULL_ACCESS  NOT CACHEABLE AND NOT BUFFERABLE 
/* Hardware Registers   */ VIRTUAL 0x8000E000 TO 0x8000FFFF PHYSICAL 0x8000E000  SMALLPAGES  NO_ACCESS    NOT CACHEABLE AND NOT BUFFERABLE 
/* Hardware Registers   */ VIRTUAL 0x80010000 TO 0x800FFFFF PHYSICAL 0x80010000  SMALLPAGES  NO_ACCESS    NOT CACHEABLE AND NOT BUFFERABLE 


/* for startup, first entry has to be patched to run from FLASH (as this table has yet to be copied to RAM) */

POSTPROCESS ENTRY 0x00000000 EQUALS 0x00000C1A