data_assign.vhd

酒吧灯光控制工程在FPGA中的实现源代码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--**************************************
ENTITY DATA_ASSIGN IS
  PORT(
     VIDEO_DATA:IN  STD_LOGIC_VECTOR(23 DOWNTO 0);
             VS:IN  STD_LOGIC;
       VIDEO_WE:IN  STD_LOGIC;
        DATA_WE:IN  STD_LOGIC;
       VIDEO_OE:IN  STD_LOGIC;
        DATA_OE:IN  STD_LOGIC;
     VIDEO_ADDR:IN  STD_LOGIC_VECTOR(13 DOWNTO 0);
      DATA_ADDR:IN  STD_LOGIC_VECTOR(13 DOWNTO 0);
      DATA_DATA:OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
           A_WE:OUT STD_LOGIC;
           B_WE:OUT STD_LOGIC;
           A_OE:OUT STD_LOGIC;
           B_OE:OUT STD_LOGIC;
         A_ADDR:OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
         B_ADDR:OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
         A_DATA:INOUT STD_LOGIC_VECTOR(23 DOWNTO 0);
         B_DATA:INOUT STD_LOGIC_VECTOR(23 DOWNTO 0)
         );
     END DATA_ASSIGN;
--******************************************
ARCHITECTURE A OF DATA_ASSIGN IS
 SIGNAL C:STD_LOGIC:='0';
 BEGIN
  PROCESS(VS)
   BEGIN
     IF VS'EVENT AND VS='1'THEN
        C<=not C;
     END IF;
   END PROCESS;
 A_ADDR<=VIDEO_ADDR WHEN C='1'ELSE
         DATA_ADDR;
 B_ADDR<=DATA_ADDR WHEN C='1'ELSE
         VIDEO_ADDR;
 A_WE<=VIDEO_WE WHEN C='1'ELSE
       DATA_WE;
 B_WE<=DATA_WE WHEN C='1'ELSE
       VIDEO_WE;
 A_OE<=VIDEO_OE WHEN C='1'ELSE
       DATA_OE;
 B_OE<=DATA_OE WHEN C='1'ELSE
       VIDEO_OE;
 A_DATA<=VIDEO_DATA WHEN C='1'ELSE
         "ZZZZZZZZZZZZZZZZZZZZZZZZ";
 B_DATA<=VIDEO_DATA WHEN C='0'ELSE
         "ZZZZZZZZZZZZZZZZZZZZZZZZ";
 DATA_DATA<=B_DATA WHEN C='1'ELSE
            A_DATA;
 END A;