📄 wdt_ac97.c
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rAC_GLBCTRL &= ~(1<<10); //PCM In Transfer PIO Mode Off
rINTSUBMSK|=(BIT_SUB_AC97);
rINTMSK|=(BIT_WDT_AC97);
UartPrintf(SHL_PRT,"\nEnd of Record!\n");
}
void AC97_MICin_DMA3(U32 MIC_Size)
{
Rec_AC97_BUF = (U32 *)(DOWN_BUF);
//IRQ Initialize
pISR_DMA3 = (unsigned)DMA3_Rec_Done;
rINTMSK=~(BIT_DMA3);
//DMA3 Initialize
rDISRC3 = ((U32)0x5B00001C); //MIC Input Data FIFO
rDISRCC3 = (1<<1) + (1<<0); //APB, Fix
rDIDST3 = (int)Rec_AC97_BUF; //Record AC97_BUF initializ
rDIDSTC3 = (0<<1) + (0<<0); //AHB, Increment
rDCON3 = (1<<31)+(0<<30)+(1<<29)+(0<<28)+(0<<27)+(5<<24)+(1<<23)+(1<<22)+(2<<20)+(MIC_Size/4);
UartPrintf(SHL_PRT,"Are you ready to record voice via MIC on SMDK2440?\n");
UartPrintf(SHL_PRT,"Press any key to start record.\n");
UartGetByte(SHL_PRT);
UartPrintf(SHL_PRT,"Recording...\n");
rDMASKTRIG3 = (0<<2) + (1<<1) + 0; //No-stop, DMA3 channel on, No-sw trigger
// Transfer data enable using AC-Link
rAC_GLBCTRL = 0x20C; // Transfer data enable using AC-Link
while(AC97_Rec_Done ==0)
{
UartPrintf(SHL_PRT,".");
Delay(3000);
//UartPrintf(SHL_PRT,"STAT3: 0x%x CURR_TC: 0x%x DCDST3: 0x%x\n", rDSTAT3&0x300000, rDSTAT3&0xfffff, rDCDST3);
}
AC97_Rec_Done = 0;
rDMASKTRIG3 = (1<<2); //DMA3 stop
rINTMSK |= BIT_DMA3;
//AC97 MIC In Channel Finish
rAC_GLBCTRL &= ~(1<<9); //MIC In Transfer Mode Off
UartPrintf(SHL_PRT,"\nEnd of Record!\n");
}
void AC97_MICin_INT(U32 PCM_Size)
{
//Record AC97_BUF initialize
Rec_AC97_BUF = (U32 *)(DOWN_BUF);
Play_AC97_BUF = Rec_AC97_BUF + 0x30;
End_AC97_BUF = (Rec_AC97_BUF + 0x30 + PCM_Size/4);
//IRQ Initialization
pISR_WDT_AC97= (unsigned)Irq_AC97_MICin;
UartPrintf(SHL_PRT,"Are you ready to record voice via MIC on SMDK2440?\n");
UartPrintf(SHL_PRT,"Press any key to start record.\n");
UartGetByte(SHL_PRT);
UartPrintf(SHL_PRT,"Recording...\n");
ClearPending(BIT_WDT_AC97);
rSUBSRCPND=(BIT_SUB_AC97);
rINTMSK=~(BIT_WDT_AC97);
rINTSUBMSK=~(BIT_SUB_AC97);
rAC_GLBCTRL = 0x1010C; //MIC In channel threshold INT enable, PIO Mode On
while(1)
{
if(PCM_In_INT_Exit == 1)
break;
}
rAC_GLBCTRL &= ~(1<<8); //MIC In Transfer PIO Mode Off
rINTSUBMSK|=(BIT_SUB_AC97);
rINTMSK|=(BIT_WDT_AC97);
UartPrintf(SHL_PRT,"\nEnd of Record!\n");
}
void AC97_CodecExit_PCMOut(void)
{
//DACs off
UartPrintf(SHL_PRT,"\n\n=>DACs off PR1\n");
AC97_Codec_Cmd(0,0x26,(1<<8)|(1<<9));
AC97_Controller_State();
UartPrintf(SHL_PRT,"AC97 Codec Powerdown Ctrl/Stat 0x26 Reg.: 0x%x\n", AC97_Codec_Cmd(1,0x26,0x0000));
//Analog off
UartPrintf(SHL_PRT,"\n=>Analog off PR2\n");
AC97_Codec_Cmd(0,0x26,(1<<8)|(1<<9)|(1<<10));
AC97_Controller_State();
UartPrintf(SHL_PRT,"AC97 Codec Powerdown Ctrl/Stat 0x26 Reg.: 0x%x\n", AC97_Codec_Cmd(1,0x26,0x0000));
//Digital I/F off
UartPrintf(SHL_PRT,"\n=>Digital I/F off PR4\n");
AC97_Codec_Cmd(0,0x26,(1<<8)|(1<<9)|(1<<10)|(1<<12));
AC97_Controller_State();
UartPrintf(SHL_PRT,"AC97 Codec Powerdown Ctrl/Stat 0x26 Reg.: 0x%x\n", AC97_Codec_Cmd(1,0x26,0x0000));
}
void AC97_CodecExit_PCMIn(U16 DACs_off)
{
//ADCs off
UartPrintf(SHL_PRT,"\n\n=>ADCs off PR0\n");
AC97_Codec_Cmd(0,0x26,(1<<8));
AC97_Controller_State();
UartPrintf(SHL_PRT,"AC97 Codec Powerdown Ctrl/Stat 0x26 Reg.: 0x%x\n", AC97_Codec_Cmd(1,0x26,0x0000));
if(DACs_off == 1)
{
//DACs off
UartPrintf(SHL_PRT,"\n\n=>DACs off PR1\n");
AC97_Codec_Cmd(0,0x26,(1<<8)|(1<<9));
AC97_Controller_State();
UartPrintf(SHL_PRT,"AC97 Codec Powerdown Ctrl/Stat 0x26 Reg.: 0x%x\n", AC97_Codec_Cmd(1,0x26,0x0000));
}
//Analog off
UartPrintf(SHL_PRT,"\n=>Analog off PR2\n");
AC97_Codec_Cmd(0,0x26,(1<<8)|(1<<9)|(1<<10));
AC97_Controller_State();
UartPrintf(SHL_PRT,"AC97 Codec Powerdown Ctrl/Stat 0x26 Reg.: 0x%x\n", AC97_Codec_Cmd(1,0x26,0x0000));
//Digital I/F off
UartPrintf(SHL_PRT,"\n=>Digital I/F off PR4\n");
AC97_Codec_Cmd(0,0x26,(1<<8)|(1<<9)|(1<<10)|(1<<12));
AC97_Controller_State();
UartPrintf(SHL_PRT,"AC97 Codec Powerdown Ctrl/Stat 0x26 Reg.: 0x%x\n", AC97_Codec_Cmd(1,0x26,0x0000));
}
void AC97_CodecExit_MICIn(U16 DACs_off)
{
//ADCs off
UartPrintf(SHL_PRT,"\n\n=>ADCs off PR0\n");
AC97_Codec_Cmd(0,0x26,(1<<8));
AC97_Controller_State();
UartPrintf(SHL_PRT,"AC97 Codec Powerdown Ctrl/Stat 0x26 Reg.: 0x%x\n", AC97_Codec_Cmd(1,0x26,0x0000));
if(DACs_off == 1)
{
//DACs off
UartPrintf(SHL_PRT,"\n\n=>DACs off PR1\n");
AC97_Codec_Cmd(0,0x26,(1<<8)|(1<<9));
AC97_Controller_State();
UartPrintf(SHL_PRT,"AC97 Codec Powerdown Ctrl/Stat 0x26 Reg.: 0x%x\n", AC97_Codec_Cmd(1,0x26,0x0000));
}
//Analog off
UartPrintf(SHL_PRT,"\n=>Analog off PR2\n");
AC97_Codec_Cmd(0,0x26,(1<<8)|(1<<9)|(1<<10));
AC97_Controller_State();
UartPrintf(SHL_PRT,"AC97 Codec Powerdown Ctrl/Stat 0x26 Reg.: 0x%x\n", AC97_Codec_Cmd(1,0x26,0x0000));
//Digital I/F off
UartPrintf(SHL_PRT,"\n=>Digital I/F off PR4\n");
AC97_Codec_Cmd(0,0x26,(1<<8)|(1<<9)|(1<<10)|(1<<12));
AC97_Controller_State();
UartPrintf(SHL_PRT,"AC97 Codec Powerdown Ctrl/Stat 0x26 Reg.: 0x%x\n", AC97_Codec_Cmd(1,0x26,0x0000));
}
U16 AC97_Select_SamplingRate(void)
{
int i;
UartPrintf(SHL_PRT,"\nSelect ADC/DAC Rate\n");
UartPrintf(SHL_PRT,"0:22.05kHz, 1:44.1kHz, 2:48kHz\n");
i = Uart_GetIntNum(SHL_PRT);
switch(i)
{
case 0:
return 22050;
break;
case 1:
return 44100;
break;
case 2:
return 48000;
break;
default:
return 48000;
break;
}
}
void AC97_Controller_State(void)
{
U08 state;
state=(U08)(rAC_GLBSTAT);
switch(state)
{
case 0:
UartPrintf(SHL_PRT,"AC97 Controller State: Idle\n");
break;
case 1:
UartPrintf(SHL_PRT,"AC97 Controller State: Init\n");
break;
case 2:
UartPrintf(SHL_PRT,"AC97 Controller State: Ready\n");
break;
case 3:
UartPrintf(SHL_PRT,"AC97 Controller State: Active\n");
break;
case 4:
UartPrintf(SHL_PRT,"AC97 Controller State: LP\n");
break;
case 5:
UartPrintf(SHL_PRT,"AC97 Controller State: Warm\n");
break;
default:
break;
}
}
void Delay_After_CommandWrite(int time)
{
// time=0: adjust the Delay function by WatchDog timer.
// time>0: the number of loop time
// Delay time resolution has 30us.
int i, adjust=0;
if(time==0)
{
time = 300;
adjust = 1;
delayLoopCount = 500;
//PCLK/1M,Watch-dog disable,1/64,interrupt disable,reset disable
rWTCON = ((PCLK/1000000-1)<<8)|(2<<3);
rWTDAT = 0xffff; //for first update
rWTCNT = 0xffff; //resolution=64us @any PCLK
rWTCON = ((PCLK/1000000-1)<<8)|(2<<3)|(1<<5); //Watch-dog timer start
}
for(;time>0;time--)
for(i=0;i<delayLoopCount;i++);
if(adjust==1)
{
rWTCON = ((PCLK/1000000-1)<<8)|(2<<3); //Watch-dog timer stop
i = 0xffff - rWTCNT; //1 count => 64us, 300*500 cycle runtime = 64*i us
delayLoopCount = 4500000/(i*64); //300*500:64*i=1*x:30 -> x=150000*30/(64*i)
}
}
void Delay_Init(void)
{
Delay(0); //Delay Time Resolution => 100us Adjust
Delay_After_CommandWrite(0); //Delay Time Resolution => 30us Adjust
}
/* ISRs */
void __irq AC97_Codec_Ready(void)
{
Delay_Init();
if ( (rAC_GLBSTAT& 0x400000))
{
Codec_Ready_Irq=1;
UartPrintf(SHL_PRT,"Codec Ready!\n");
rAC_GLBCTRL &= ~(0x400000); // codec ready interrupt disable
}
rSUBSRCPND=(BIT_SUB_AC97);
ClearPending(BIT_WDT_AC97);
rINTSUBMSK &= ~(BIT_SUB_AC97);
rINTMSK &=~(BIT_WDT_AC97);
}
void __irq DMA1_Play_Done(void)
{
ClearPending(BIT_DMA1);
UartPrintf(SHL_PRT,"\n~~~");
}
void __irq DMA2_Rec_Done(void)
{
ClearPending(BIT_DMA2);
AC97_Rec_Done = 1;
}
void __irq DMA3_Rec_Done(void)
{
ClearPending(BIT_DMA3);
AC97_Rec_Done = 1;
}
void __irq Irq_AC97_PCMout(void)
{
U32 i, AC97_Stat;
rINTMSK |=(BIT_WDT_AC97);
rINTSUBMSK|=(BIT_SUB_AC97);
AC97_Stat = rAC_GLBSTAT;
if (AC97_Stat & AC97_PCM_OUT_THRESHOLD)
{
for(i=0; i<PCM_OUT_TRIGGER; i++)
{
rAC_PCMDATA = *(Play_AC97_BUF++);
if(Play_AC97_BUF == End_AC97_BUF)
break;
}
}
if(Play_AC97_BUF == End_AC97_BUF)
{
rAC_GLBCTRL &= ~(0x40000); //PCM Out channel threshold INT disable
PCM_Out_INT_Exit =1;
}
rSUBSRCPND=(BIT_SUB_AC97);
ClearPending(BIT_WDT_AC97);
rINTSUBMSK &= ~(BIT_SUB_AC97);
rINTMSK &= ~(BIT_WDT_AC97);
}
void __irq Irq_AC97_PCMin(void)
{
U32 AC97_Stat, i;
rINTMSK |=(BIT_WDT_AC97);
rINTSUBMSK|=(BIT_SUB_AC97);
AC97_Stat = rAC_GLBSTAT;
if (AC97_Stat & AC97_PCM_IN_THRESHOLD)
{
for(i=0; i<PCM_IN_TRIGGER; i++)
{
*(Play_AC97_BUF++) = rAC_PCMDATA;
if(Play_AC97_BUF == End_AC97_BUF)
break;
}
}
if(Play_AC97_BUF == End_AC97_BUF)
{
rAC_GLBCTRL &= ~(1<<17); //PCM In channel threshold INT disable
PCM_In_INT_Exit =1;
}
rSUBSRCPND=(BIT_SUB_AC97);
ClearPending(BIT_WDT_AC97);
rINTSUBMSK &= ~(BIT_SUB_AC97);
rINTMSK &= ~(BIT_WDT_AC97);
}
void __irq Irq_AC97_MICin(void)
{
U32 AC97_Stat, i;
rINTMSK |=(BIT_WDT_AC97);
rINTSUBMSK|=(BIT_SUB_AC97);
AC97_Stat = rAC_GLBSTAT;
if (AC97_Stat & AC97_MIC_IN_THRESHOLD)
{
for(i=0; i<PCM_IN_TRIGGER; i++)
{
*(Play_AC97_BUF++) = rAC_MICDATA;
if(Play_AC97_BUF == End_AC97_BUF)
break;
}
}
if(Play_AC97_BUF == End_AC97_BUF)
{
rAC_GLBCTRL &= ~(1<<16); //PCM In channel threshold INT disable
PCM_In_INT_Exit =1;
}
rSUBSRCPND=(BIT_SUB_AC97);
ClearPending(BIT_WDT_AC97);
rINTSUBMSK &= ~(BIT_SUB_AC97);
rINTMSK &= ~(BIT_WDT_AC97);
}
void __irq RxInt(void)
{
rSUBSRCPND = BIT_SUB_RXD1;
rSUBSRCPND;
ClearPending(BIT_UART1);
*AC97_temp ++= RdURXH1();
}
void __irq Muting(void)
{
ClearPending(BIT_EINT0);
if(AC97_mute) //AC97_mute
{
AC97_mute = 0;
AC97_Codec_Cmd(0,0x04, Output_Volume|0x8000);
UartPrintf(SHL_PRT,"\nAC97 Mute On...\n");
}
else //No AC97_mute
{
AC97_mute = 1;
AC97_Codec_Cmd(0,0x04, Output_Volume& ~(0x8000));
UartPrintf(SHL_PRT,"\nAC97 Mute Off...\n");
}
}
#endif //__WDT_AC97_C__
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