intprg.c

这是关于NEC公司产的SH2系列芯片的几个例子程序,对这几个熟了,就很有利于基于其上的开发的展开

/***********************************************************************/
/*                                                                     */
/*  FILE        :intprg.c                                              */
/*  DATE        :Fri, Feb 17, 2006                                     */
/*  DESCRIPTION :Interrupt Program                                     */
/*  CPU TYPE    :SH7144F                                               */
/*                                                                     */
/*  This file is generated by Renesas Project Generator (Ver.4.0).     */
/*                                                                     */
/***********************************************************************/
                  


#include <machine.h>
#include "vect.h"
#include "iodefine.h"
#pragma section IntPRG
// 4 Illegal code
void INT_Illegal_code(void){/* sleep(); */}
// 5 Reserved

// 6 Illegal slot
void INT_Illegal_slot(void){/* sleep(); */}
// 7 Reserved

// 8 Reserved

// 9 CPU Address error
void INT_CPU_Address(void){/* sleep(); */}
// 10 DMAC/DTC Address error
void INT_DTC_Address(void){/* sleep(); */}
// 11 NMI
void INT_NMI(void){/* sleep(); */}
// 12 User breakpoint trap
void INT_User_Break(void){/* sleep(); */}
// 13 Reserved

// 14 H-UDI
void INT_H_UDI(void){/* sleep(); */}
// 15 Reserved

// 16 Reserved

// 17 Reserved

// 18 Reserved

// 19 Reserved

// 20 Reserved

// 21 Reserved

// 22 Reserved

// 23 Reserved

// 24 Reserved

// 25 Reserved

// 26 Reserved

// 27 Reserved

// 28 Reserved

// 29 Reserved

// 30 Reserved

// 31 Reserved

// 32 TRAPA (User Vecter)
void INT_TRAPA32(void){/* sleep(); */}
// 33 TRAPA (User Vecter)
void INT_TRAPA33(void){/* sleep(); */}
// 34 TRAPA (User Vecter)
void INT_TRAPA34(void){/* sleep(); */}
// 35 TRAPA (User Vecter)
void INT_TRAPA35(void){/* sleep(); */}
// 36 TRAPA (User Vecter)
void INT_TRAPA36(void){/* sleep(); */}
// 37 TRAPA (User Vecter)
void INT_TRAPA37(void){/* sleep(); */}
// 38 TRAPA (User Vecter)
void INT_TRAPA38(void){/* sleep(); */}
// 39 TRAPA (User Vecter)
void INT_TRAPA39(void){/* sleep(); */}
// 40 TRAPA (User Vecter)
void INT_TRAPA40(void){/* sleep(); */}
// 41 TRAPA (User Vecter)
void INT_TRAPA41(void){/* sleep(); */}
// 42 TRAPA (User Vecter)
void INT_TRAPA42(void){/* sleep(); */}
// 43 TRAPA (User Vecter)
void INT_TRAPA43(void){/* sleep(); */}
// 44 TRAPA (User Vecter)
void INT_TRAPA44(void){/* sleep(); */}
// 45 TRAPA (User Vecter)
void INT_TRAPA45(void){/* sleep(); */}
// 46 TRAPA (User Vecter)
void INT_TRAPA46(void){/* sleep(); */}
// 47 TRAPA (User Vecter)
void INT_TRAPA47(void){/* sleep(); */}
// 48 TRAPA (User Vecter)
void INT_TRAPA48(void){/* sleep(); */}
// 49 TRAPA (User Vecter)
void INT_TRAPA49(void){/* sleep(); */}
// 50 TRAPA (User Vecter)
void INT_TRAPA50(void){/* sleep(); */}
// 51 TRAPA (User Vecter)
void INT_TRAPA51(void){/* sleep(); */}
// 52 TRAPA (User Vecter)
void INT_TRAPA52(void){/* sleep(); */}
// 53 TRAPA (User Vecter)
void INT_TRAPA53(void){/* sleep(); */}
// 54 TRAPA (User Vecter)
void INT_TRAPA54(void){/* sleep(); */}
// 55 TRAPA (User Vecter)
void INT_TRAPA55(void){/* sleep(); */}
// 56 TRAPA (User Vecter)
void INT_TRAPA56(void){/* sleep(); */}
// 57 TRAPA (User Vecter)
void INT_TRAPA57(void){/* sleep(); */}
// 58 TRAPA (User Vecter)
void INT_TRAPA58(void){/* sleep(); */}
// 59 TRAPA (User Vecter)
void INT_TRAPA59(void){/* sleep(); */}
// 60 TRAPA (User Vecter)
void INT_TRAPA60(void){/* sleep(); */}
// 61 TRAPA (User Vecter)
void INT_TRAPA61(void){/* sleep(); */}
// 62 TRAPA (User Vecter)
void INT_TRAPA62(void){/* sleep(); */}
// 63 TRAPA (User Vecter)
void INT_TRAPA63(void){/* sleep(); */}
// 64 Interrupt IRQ0
void INT_IRQ0(void){/* sleep(); */}
// 65 Interrupt IRQ1
void INT_IRQ1(void){/* sleep(); */}
// 66 Interrupt IRQ2
void INT_IRQ2(void){/* sleep(); */}
// 67 Interrupt IRQ3
void INT_IRQ3(void){/* sleep(); */}
// 68 Interrupt IRQ4
void INT_IRQ4(void){/* sleep(); */}
// 69 Interrupt IRQ5
void INT_IRQ5(void){/* sleep(); */}
// 70 Interrupt IRQ6
void INT_IRQ6(void){/* sleep(); */}
// 71 Interrupt IRQ7
void INT_IRQ7(void){/* sleep(); */}
// 72 DMAC DEI0
void INT_DMAC_DEI0(void){/* sleep(); */}
// 73 Reserved

// 74 Reserved

// 75 Reserved

// 76 DMAC DEI1
void INT_DMAC_DEI1(void){/* sleep(); */}
// 77 Reserved

// 78 Reserved

// 79 Reserved

// 80 DMAC DEI2
void INT_DMAC_DEI2(void){/* sleep(); */}
// 81 Reserved

// 82 Reserved

// 83 Reserved

// 84 DMAC DEI3
void INT_DMAC_DEI3(void){/* sleep(); */}
// 85 Reserved

// 86 Reserved

// 87 Reserved

// 88 MTU0 TGIA0
void INT_MTU0_TGIA0(void){/* sleep(); */}
// 89 MTU0 TGIB0
void INT_MTU0_TGIB0(void){/* sleep(); */}
// 90 MTU0 TGIC0
void INT_MTU0_TGIC0(void){/* sleep(); */}
// 91 MTU0 TGID0
void INT_MTU0_TGID0(void){/* sleep(); */}
// 92 MTU0 TCIV0
void INT_MTU0_TCIV0(void){/* sleep(); */}
// 93 Reserved

// 94 Reserved

// 95 Reserved

// 96 MTU1 TGIA1
void INT_MTU1_TGIA1(void){/* sleep(); */}
// 97 MTU1 TGIB1
void INT_MTU1_TGIB1(void){/* sleep(); */}
// 98 Reserved

// 99 Reserved

// 100 MTU1 TCIV1
void INT_MTU1_TCIV1(void){/* sleep(); */}
// 101 MTU1 TCIU1
void INT_MTU1_TCIU1(void){/* sleep(); */}
// 102 Reserved

// 103 Reserved

// 104 MTU2 TGIA2
void INT_MTU2_TGIA2(void){/* sleep(); */}
// 105 MTU2 TGIB2
void INT_MTU2_TGIB2(void){/* sleep(); */}
// 106 Reserved

// 107 Reserved

// 108 MTU2 TCIV2
void INT_MTU2_TCIV2(void){/* sleep(); */}
// 109 MTU2 TCIU2
void INT_MTU2_TCIU2(void){/* sleep(); */}
// 110 Reserved

// 111 Reserved

// 112 MTU3 TGIA3
void INT_MTU3_TGIA3(void){/* sleep(); */}
// 113 MTU3 TGIB3
void INT_MTU3_TGIB3(void){/* sleep(); */}
// 114 MTU3 TGIC3
void INT_MTU3_TGIC3(void){/* sleep(); */}
// 115 MTU3 TGID3
void INT_MTU3_TGID3(void){/* sleep(); */}
// 116 MTU3 TCIV3
void INT_MTU3_TCIV3(void){/* sleep(); */}
// 117 Reserved

// 118 Reserved

// 119 Reserved

// 120 MTU4 TGIA4
void INT_MTU4_TGIA4(void){/* sleep(); */}
// 121 MTU4 TGIB4
void INT_MTU4_TGIB4(void){/* sleep(); */}
// 122 MTU4 TGIC4
void INT_MTU4_TGIC4(void){/* sleep(); */}
// 123 MTU4 TGID4
void INT_MTU4_TGID4(void){/* sleep(); */}
// 124 MTU4 TCIV4
void INT_MTU4_TCIV4(void){/* sleep(); */}
// 125 Reserved

// 126 Reserved

// 127 Reserved

// 128 SCI0 ERI0
void INT_SCI0_ERI0(void){/* sleep(); */}
// 129 SCI0 RXI0
void INT_SCI0_RXI0(void){/* sleep(); */}
// 130 SCI0 TXI0
void INT_SCI0_TXI0(void){/* sleep(); */}
// 131 SCI0 TEI0
void INT_SCI0_TEI0(void){/* sleep(); */}
// 132 SCI1 ERI1
void INT_SCI1_ERI1(void){/* sleep(); */}
// 133 SCI1 RXI1
void INT_SCI1_RXI1(void){/* sleep(); */}
// 134 SCI1 TXI1
void INT_SCI1_TXI1(void){/* sleep(); */}
// 135 SCI1 TEI1
void INT_SCI1_TEI1(void){/* sleep(); */}
// 136 A/D ADI0
void INT_ADI0(void){/* sleep(); */}
// 137 A/D ADI1
void INT_ADI1(void){/* sleep(); */}
// 138 Reserved

// 139 Reserved

// 140 DTC SWDTEND
void INT_DTC_SWDTEND(void){/* sleep(); */}
// 141 Reserved

// 142 Reserved

// 143 Reserved

// 144 CMT CMT0
#pragma interrupt INT_CMT_CMT0
void INT_CMT_CMT0(void){
	extern int cont;
	extern int sec,sec1,sec2,sec3;
	CMT0.CMCSR.BIT.CMF = 0;
	cont++;
	if(cont >= 1000){
		PE.DRL.BIT.B15 = ~PE.DRL.BIT.B15;
		cont =0;
		sec++;
		}
	if(sec >= 10){
		sec=0;
		sec1++;
		if(sec1 >= 6){
			sec1 = 0;
			sec2++;
			if(sec2 >= 10){
				sec2 = 0;
				sec3++;
				if(sec3 >= 6){
					sec3 = 0;
					}
				}
			}
		}
	}
// 145 Reserved

// 146 Reserved

// 147 Reserved

// 148 CMT CMT1
void INT_CMT_CMT1(void){/*sleep();*/}
// 149 Reserved

// 150 Reserved

// 151 Reserved

// 152 WDT ITI
void INT_WDT_ITI(void){/* sleep(); */}
// 153 BSC CMI
void INT_BSC_CMI(void){/* sleep(); */}
// 154 Reserved

// 155 Reserved

// 156 I/O MTUOEI
void INT_MTUOEI(void){/* sleep(); */}
// 157 Reserved

// 158 Reserved

// 159 Reserved

// 160 Reserved

// 161 Reserved

// 162 Reserved

// 163 Reserved

// 164 Reserved

// 165 Reserved

// 166 Reserved

// 167 Reserved

// 168 SCI2 ERI2
void INT_SCI2_ERI2(void){/* sleep(); */}
// 169 SCI2 RXI2
void INT_SCI2_RXI2(void){/* sleep(); */}
// 170 SCI2 TXI2
void INT_SCI2_TXI2(void){/* sleep(); */}
// 171 SCI2 TEI2
void INT_SCI2_TEI2(void){/* sleep(); */}
// 172 SCI3 ERI3
void INT_SCI3_ERI3(void){/* sleep(); */}
// 173 SCI3 RXI3
void INT_SCI3_RXI3(void){/* sleep(); */}
// 174 SCI3 TXI3
void INT_SCI3_TXI3(void){/* sleep(); */}
// 175 SCI3 TEI3
void INT_SCI3_TEI3(void){/* sleep(); */}
// 176 Reserved

// 177 Reserved

// 178 Reserved

// 179 Reserved

// 180 Reserved

// 181 Reserved

// 182 Reserved

// 183 Reserved

// 184 Reserved

// 185 Reserved

// 186 Reserved

// 187 Reserved

// 188 Reserved

// 189 Reserved

// 190 Reserved

// 191 Reserved

// 192 IIC IIC0RM
void INT_IIC0RM(void){/* sleep(); */}
// 193 Reserved

// 194 Reserved

// 195 Reserved

// 196 Reserved

// 197 Reserved

// 198 Reserved

// 199 Reserved

// 200 Reserved

// 201 Reserved

// 202 Reserved

// 203 Reserved

// 204 Reserved

// 205 Reserved

// 206 Reserved

// 207 Reserved

// 208 Reserved

// 209 Reserved

// 210 Reserved

// 211 Reserved

// 212 Reserved

// 213 Reserved

// 214 Reserved

// 215 Reserved

// 216 Reserved

// 217 Reserved

// 218 Reserved

// 219 Reserved

// 220 Reserved

// 221 Reserved

// 222 Reserved

// 223 Reserved

// 224 Reserved

// 225 Reserved

// 226 Reserved

// 227 Reserved

// 228 Reserved

// 229 Reserved

// 230 Reserved

// 231 Reserved

// 232 Reserved

// 233 Reserved

// 234 Reserved

// 235 Reserved

// 236 Reserved

// 237 Reserved

// 238 Reserved

// 239 Reserved

// 240 Reserved

// 241 Reserved

// 242 Reserved

// 243 Reserved

// 244 Reserved

// 245 Reserved

// 246 Reserved

// 247 Reserved

// 248 Reserved

// 249 Reserved

// 250 Reserved

// 251 Reserved

// 252 Reserved

// 253 Reserved

// 254 Reserved

// 255 Reserved


// Dummy
void Dummy(void){/* sleep(); */}