vecttbl.c

这是关于NEC公司产的SH2系列芯片的几个例子程序,对这几个熟了,就很有利于基于其上的开发的展开

/***********************************************************************/
/*                                                                     */
/*  FILE        :vecttbl.c                                             */
/*  DATE        :Fri, Feb 17, 2006                                     */
/*  DESCRIPTION :Initialize of Vector Table                            */
/*  CPU TYPE    :SH7144F                                               */
/*                                                                     */
/*  This file is generated by Renesas Project Generator (Ver.4.0).     */
/*                                                                     */
/***********************************************************************/
                  


#include "vect.h"

#pragma section VECTTBL

void *RESET_Vectors[] = {
//;<<VECTOR DATA START (POWER ON RESET)>>
//;0 Power On Reset PC
(void*)PowerON_Reset_PC,                                                                                                                            
//;<<VECTOR DATA END (POWER ON RESET)>>
// 1 Power On Reset SP
    __secend("S"),
//;<<VECTOR DATA START (MANUAL RESET)>>
//;2 Manual Reset PC
(void*)Manual_Reset_PC,                                                                                                                             
//;<<VECTOR DATA END (MANUAL RESET)>>
// 3 Manual Reset SP
    __secend("S")

};
#pragma section INTTBL
void *INT_Vectors[] = {
// 4 Illegal code
    (void*) INT_Illegal_code,
// 5 Reserved
    (void*) 0,
// 6 Illegal slot
    (void*) INT_Illegal_slot,
// 7 Reserved
    (void*) 0,
// 8 Reserved
    (void*) 0,
// 9 CPU Address error
    (void*) INT_CPU_Address,
// 10 DMAC/DTC Address error
    (void*) INT_DTC_Address,
// 11 NMI
    (void*) INT_NMI,
// 12 User breakpoint trap
    (void*) INT_User_Break,
// 13 Reserved
    (void*) 0,
// 14 H-UDI
    (void*) INT_H_UDI,
// 15 Reserved
    (void*) 0,
// 16 Reserved
    (void*) 0,
// 17 Reserved
    (void*) 0,
// 18 Reserved
    (void*) 0,
// 19 Reserved
    (void*) 0,
// 20 Reserved
    (void*) 0,
// 21 Reserved
    (void*) 0,
// 22 Reserved
    (void*) 0,
// 23 Reserved
    (void*) 0,
// 24 Reserved
    (void*) 0,
// 25 Reserved
    (void*) 0,
// 26 Reserved
    (void*) 0,
// 27 Reserved
    (void*) 0,
// 28 Reserved
    (void*) 0,
// 29 Reserved
    (void*) 0,
// 30 Reserved
    (void*) 0,
// 31 Reserved
    (void*) 0,
// 32 TRAPA (User Vecter)
    (void*) INT_TRAPA32,
// 33 TRAPA (User Vecter)
    (void*) INT_TRAPA33,
// 34 TRAPA (User Vecter)
    (void*) INT_TRAPA34,
// 35 TRAPA (User Vecter)
    (void*) INT_TRAPA35,
// 36 TRAPA (User Vecter)
    (void*) INT_TRAPA36,
// 37 TRAPA (User Vecter)
    (void*) INT_TRAPA37,
// 38 TRAPA (User Vecter)
    (void*) INT_TRAPA38,
// 39 TRAPA (User Vecter)
    (void*) INT_TRAPA39,
// 40 TRAPA (User Vecter)
    (void*) INT_TRAPA40,
// 41 TRAPA (User Vecter)
    (void*) INT_TRAPA41,
// 42 TRAPA (User Vecter)
    (void*) INT_TRAPA42,
// 43 TRAPA (User Vecter)
    (void*) INT_TRAPA43,
// 44 TRAPA (User Vecter)
    (void*) INT_TRAPA44,
// 45 TRAPA (User Vecter)
    (void*) INT_TRAPA45,
// 46 TRAPA (User Vecter)
    (void*) INT_TRAPA46,
// 47 TRAPA (User Vecter)
    (void*) INT_TRAPA47,
// 48 TRAPA (User Vecter)
    (void*) INT_TRAPA48,
// 49 TRAPA (User Vecter)
    (void*) INT_TRAPA49,
// 50 TRAPA (User Vecter)
    (void*) INT_TRAPA50,
// 51 TRAPA (User Vecter)
    (void*) INT_TRAPA51,
// 52 TRAPA (User Vecter)
    (void*) INT_TRAPA52,
// 53 TRAPA (User Vecter)
    (void*) INT_TRAPA53,
// 54 TRAPA (User Vecter)
    (void*) INT_TRAPA54,
// 55 TRAPA (User Vecter)
    (void*) INT_TRAPA55,
// 56 TRAPA (User Vecter)
    (void*) INT_TRAPA56,
// 57 TRAPA (User Vecter)
    (void*) INT_TRAPA57,
// 58 TRAPA (User Vecter)
    (void*) INT_TRAPA58,
// 59 TRAPA (User Vecter)
    (void*) INT_TRAPA59,
// 60 TRAPA (User Vecter)
    (void*) INT_TRAPA60,
// 61 TRAPA (User Vecter)
    (void*) INT_TRAPA61,
// 62 TRAPA (User Vecter)
    (void*) INT_TRAPA62,
// 63 TRAPA (User Vecter)
    (void*) INT_TRAPA63,
// 64 Interrupt IRQ0
    (void*) INT_IRQ0,
// 65 Interrupt IRQ1
    (void*) INT_IRQ1,
// 66 Interrupt IRQ2
    (void*) INT_IRQ2,
// 67 Interrupt IRQ3
    (void*) INT_IRQ3,
// 68 Interrupt IRQ4
    (void*) INT_IRQ4,
// 69 Interrupt IRQ5
    (void*) INT_IRQ5,
// 70 Interrupt IRQ6
    (void*) INT_IRQ6,
// 71 Interrupt IRQ7
    (void*) INT_IRQ7,
// 72 DMAC DEI0
    (void*) INT_DMAC_DEI0,
// 73 Reserved
    (void*) 0,
// 74 Reserved
    (void*) 0,
// 75 Reserved
    (void*) 0,
// 76 DMAC DEI1
    (void*) INT_DMAC_DEI1,
// 77 Reserved
    (void*) 0,
// 78 Reserved
    (void*) 0,
// 79 Reserved
    (void*) 0,
// 80 DMAC DEI2
    (void*) INT_DMAC_DEI2,
// 81 Reserved
    (void*) 0,
// 82 Reserved
    (void*) 0,
// 83 Reserved
    (void*) 0,
// 84 DMAC DEI3
    (void*) INT_DMAC_DEI3,
// 85 Reserved
    (void*) 0,
// 86 Reserved
    (void*) 0,
// 87 Reserved
    (void*) 0,
// 88 MTU0 TGIA0
    (void*) INT_MTU0_TGIA0,
// 89 MTU0 TGIB0
    (void*) INT_MTU0_TGIB0,
// 90 MTU0 TGIC0
    (void*) INT_MTU0_TGIC0,
// 91 MTU0 TGID0
    (void*) INT_MTU0_TGID0,
// 92 MTU0 TCIV0
    (void*) INT_MTU0_TCIV0,
// 93 Reserved
    (void*) 0,
// 94 Reserved
    (void*) 0,
// 95 Reserved
    (void*) 0,
// 96 MTU1 TGIA1
    (void*) INT_MTU1_TGIA1,
// 97 MTU1 TGIB1
    (void*) INT_MTU1_TGIB1,
// 98 Reserved
    (void*) 0,
// 99 Reserved
    (void*) 0,
// 100 MTU1 TCIV1
    (void*) INT_MTU1_TCIV1,
// 101 MTU1 TCIU1
    (void*) INT_MTU1_TCIU1,
// 102 Reserved
    (void*) 0,
// 103 Reserved
    (void*) 0,
// 104 MTU2 TGIA2
    (void*) INT_MTU2_TGIA2,
// 105 MTU2 TGIB2
    (void*) INT_MTU2_TGIB2,
// 106 Reserved
    (void*) 0,
// 107 Reserved
    (void*) 0,
// 108 MTU2 TCIV2
    (void*) INT_MTU2_TCIV2,
// 109 MTU2 TCIU2
    (void*) INT_MTU2_TCIU2,
// 110 Reserved
    (void*) 0,
// 111 Reserved
    (void*) 0,
// 112 MTU3 TGIA3
    (void*) INT_MTU3_TGIA3,
// 113 MTU3 TGIB3
    (void*) INT_MTU3_TGIB3,
// 114 MTU3 TGIC3
    (void*) INT_MTU3_TGIC3,
// 115 MTU3 TGID3
    (void*) INT_MTU3_TGID3,
// 116 MTU3 TCIV3
    (void*) INT_MTU3_TCIV3,
// 117 Reserved
    (void*) 0,
// 118 Reserved
    (void*) 0,
// 119 Reserved
    (void*) 0,
// 120 MTU4 TGIA4
    (void*) INT_MTU4_TGIA4,
// 121 MTU4 TGIB4
    (void*) INT_MTU4_TGIB4,
// 122 MTU4 TGIC4
    (void*) INT_MTU4_TGIC4,
// 123 MTU4 TGID4
    (void*) INT_MTU4_TGID4,
// 124 MTU4 TCIV4
    (void*) INT_MTU4_TCIV4,
// 125 Reserved
    (void*) 0,
// 126 Reserved
    (void*) 0,
// 127 Reserved
    (void*) 0,
// 128 SCI0 ERI0
    (void*) INT_SCI0_ERI0,
// 129 SCI0 RXI0
    (void*) INT_SCI0_RXI0,
// 130 SCI0 TXI0
    (void*) INT_SCI0_TXI0,
// 131 SCI0 TEI0
    (void*) INT_SCI0_TEI0,
// 132 SCI1 ERI1
    (void*) INT_SCI1_ERI1,
// 133 SCI1 RXI1
    (void*) INT_SCI1_RXI1,
// 134 SCI1 TXI1
    (void*) INT_SCI1_TXI1,
// 135 SCI1 TEI1
    (void*) INT_SCI1_TEI1,
// 136 A/D ADI0
    (void*) INT_ADI0,
// 137 A/D ADI1
    (void*) INT_ADI1,
// 138 Reserved
    (void*) 0,
// 139 Reserved
    (void*) 0,
// 140 DTC SWDTEND
    (void*) INT_DTC_SWDTEND,
// 141 Reserved
    (void*) 0,
// 142 Reserved
    (void*) 0,
// 143 Reserved
    (void*) 0,
// 144 CMT CMT0
    (void*) INT_CMT_CMT0,
// 145 Reserved
    (void*) 0,
// 146 Reserved
    (void*) 0,
// 147 Reserved
    (void*) 0,
// 148 CMT CMT1
    (void*) INT_CMT_CMT1,
// 149 Reserved
    (void*) 0,
// 150 Reserved
    (void*) 0,
// 151 Reserved
    (void*) 0,
// 152 WDT ITI
    (void*) INT_WDT_ITI,
// 153 BSC CMI
    (void*) INT_BSC_CMI,
// 154 Reserved
    (void*) 0,
// 155 Reserved
    (void*) 0,
// 156 I/O MTUOEI
    (void*) INT_MTUOEI,
// 157 Reserved
    (void*) 0,
// 158 Reserved
    (void*) 0,
// 159 Reserved
    (void*) 0,
// 160 Reserved
    (void*) 0,
// 161 Reserved
    (void*) 0,
// 162 Reserved
    (void*) 0,
// 163 Reserved
    (void*) 0,
// 164 Reserved
    (void*) 0,
// 165 Reserved
    (void*) 0,
// 166 Reserved
    (void*) 0,
// 167 Reserved
    (void*) 0,
// 168 SCI2 ERI2
    (void*) INT_SCI2_ERI2,
// 169 SCI2 RXI2
    (void*) INT_SCI2_RXI2,
// 170 SCI2 TXI2
    (void*) INT_SCI2_TXI2,
// 171 SCI2 TEI2
    (void*) INT_SCI2_TEI2,
// 172 SCI3 ERI3
    (void*) INT_SCI3_ERI3,
// 173 SCI3 RXI3
    (void*) INT_SCI3_RXI3,
// 174 SCI3 TXI3
    (void*) INT_SCI3_TXI3,
// 175 SCI3 TEI3
    (void*) INT_SCI3_TEI3,
// 176 Reserved
    (void*) 0,
// 177 Reserved
    (void*) 0,
// 178 Reserved
    (void*) 0,
// 179 Reserved
    (void*) 0,
// 180 Reserved
    (void*) 0,
// 181 Reserved
    (void*) 0,
// 182 Reserved
    (void*) 0,
// 183 Reserved
    (void*) 0,
// 184 Reserved
    (void*) 0,
// 185 Reserved
    (void*) 0,
// 186 Reserved
    (void*) 0,
// 187 Reserved
    (void*) 0,
// 188 Reserved
    (void*) 0,
// 189 Reserved
    (void*) 0,
// 190 Reserved
    (void*) 0,
// 191 Reserved
    (void*) 0,
// 192 IIC IIC0RM
    (void*) INT_IIC0RM,
// 193 Reserved
    (void*) 0,
// 194 Reserved
    (void*) 0,
// 195 Reserved
    (void*) 0,
// 196 Reserved
    (void*) 0,
// 197 Reserved
    (void*) 0,
// 198 Reserved
    (void*) 0,
// 199 Reserved
    (void*) 0,
// 200 Reserved
    (void*) 0,
// 201 Reserved
    (void*) 0,
// 202 Reserved
    (void*) 0,
// 203 Reserved
    (void*) 0,
// 204 Reserved
    (void*) 0,
// 205 Reserved
    (void*) 0,
// 206 Reserved
    (void*) 0,
// 207 Reserved
    (void*) 0,
// 208 Reserved
    (void*) 0,
// 209 Reserved
    (void*) 0,
// 210 Reserved
    (void*) 0,
// 211 Reserved
    (void*) 0,
// 212 Reserved
    (void*) 0,
// 213 Reserved
    (void*) 0,
// 214 Reserved
    (void*) 0,
// 215 Reserved
    (void*) 0,
// 216 Reserved
    (void*) 0,
// 217 Reserved
    (void*) 0,
// 218 Reserved
    (void*) 0,
// 219 Reserved
    (void*) 0,
// 220 Reserved
    (void*) 0,
// 221 Reserved
    (void*) 0,
// 222 Reserved
    (void*) 0,
// 223 Reserved
    (void*) 0,
// 224 Reserved
    (void*) 0,
// 225 Reserved
    (void*) 0,
// 226 Reserved
    (void*) 0,
// 227 Reserved
    (void*) 0,
// 228 Reserved
    (void*) 0,
// 229 Reserved
    (void*) 0,
// 230 Reserved
    (void*) 0,
// 231 Reserved
    (void*) 0,
// 232 Reserved
    (void*) 0,
// 233 Reserved
    (void*) 0,
// 234 Reserved
    (void*) 0,
// 235 Reserved
    (void*) 0,
// 236 Reserved
    (void*) 0,
// 237 Reserved
    (void*) 0,
// 238 Reserved
    (void*) 0,
// 239 Reserved
    (void*) 0,
// 240 Reserved
    (void*) 0,
// 241 Reserved
    (void*) 0,
// 242 Reserved
    (void*) 0,
// 243 Reserved
    (void*) 0,
// 244 Reserved
    (void*) 0,
// 245 Reserved
    (void*) 0,
// 246 Reserved
    (void*) 0,
// 247 Reserved
    (void*) 0,
// 248 Reserved
    (void*) 0,
// 249 Reserved
    (void*) 0,
// 250 Reserved
    (void*) 0,
// 251 Reserved
    (void*) 0,
// 252 Reserved
    (void*) 0,
// 253 Reserved
    (void*) 0,
// 254 Reserved
    (void*) 0,
// 255 Reserved
    (void*) 0
};