📄 fxinst.cpp

📁 SFC游戏模拟器 snes9x 1.43 的原代码
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static void fx_sub_r9() { FX_SUB(9); }static void fx_sub_r10() { FX_SUB(10); }static void fx_sub_r11() { FX_SUB(11); }static void fx_sub_r12() { FX_SUB(12); }static void fx_sub_r13() { FX_SUB(13); }static void fx_sub_r14() { FX_SUB(14); }static void fx_sub_r15() { FX_SUB(15); }/* 60-6f(ALT1) - sbc rn - subtract with carry, register - register */#define FX_SBC(reg) \int32 s = SUSEX16(SREG) - SUSEX16(GSU.avReg[reg]) - (SUSEX16(GSU.vCarry^1)); \GSU.vCarry = s >= 0; \GSU.vOverflow = (SREG ^ GSU.avReg[reg]) & (SREG ^ s) & 0x8000; \GSU.vSign = s; \GSU.vZero = s; \R15++; DREG = s; \TESTR14; \CLRFLAGSstatic void fx_sbc_r0() { FX_SBC(0); }static void fx_sbc_r1() { FX_SBC(1); }static void fx_sbc_r2() { FX_SBC(2); }static void fx_sbc_r3() { FX_SBC(3); }static void fx_sbc_r4() { FX_SBC(4); }static void fx_sbc_r5() { FX_SBC(5); }static void fx_sbc_r6() { FX_SBC(6); }static void fx_sbc_r7() { FX_SBC(7); }static void fx_sbc_r8() { FX_SBC(8); }static void fx_sbc_r9() { FX_SBC(9); }static void fx_sbc_r10() { FX_SBC(10); }static void fx_sbc_r11() { FX_SBC(11); }static void fx_sbc_r12() { FX_SBC(12); }static void fx_sbc_r13() { FX_SBC(13); }static void fx_sbc_r14() { FX_SBC(14); }static void fx_sbc_r15() { FX_SBC(15); }/* 60-6f(ALT2) - sub #n - subtract, register - immediate */#define FX_SUB_I(imm) \int32 s = SUSEX16(SREG) - imm; \GSU.vCarry = s >= 0; \GSU.vOverflow = (SREG ^ imm) & (SREG ^ s) & 0x8000; \GSU.vSign = s; \GSU.vZero = s; \R15++; DREG = s; \TESTR14; \CLRFLAGSstatic void fx_sub_i0() { FX_SUB_I(0); }static void fx_sub_i1() { FX_SUB_I(1); }static void fx_sub_i2() { FX_SUB_I(2); }static void fx_sub_i3() { FX_SUB_I(3); }static void fx_sub_i4() { FX_SUB_I(4); }static void fx_sub_i5() { FX_SUB_I(5); }static void fx_sub_i6() { FX_SUB_I(6); }static void fx_sub_i7() { FX_SUB_I(7); }static void fx_sub_i8() { FX_SUB_I(8); }static void fx_sub_i9() { FX_SUB_I(9); }static void fx_sub_i10() { FX_SUB_I(10); }static void fx_sub_i11() { FX_SUB_I(11); }static void fx_sub_i12() { FX_SUB_I(12); }static void fx_sub_i13() { FX_SUB_I(13); }static void fx_sub_i14() { FX_SUB_I(14); }static void fx_sub_i15() { FX_SUB_I(15); }/* 60-6f(ALT3) - cmp rn - compare, register, register */#define FX_CMP(reg) \int32 s = SUSEX16(SREG) - SUSEX16(GSU.avReg[reg]); \GSU.vCarry = s >= 0; \GSU.vOverflow = (SREG ^ GSU.avReg[reg]) & (SREG ^ s) & 0x8000; \GSU.vSign = s; \GSU.vZero = s; \R15++; \CLRFLAGS;static void fx_cmp_r0() { FX_CMP(0); }static void fx_cmp_r1() { FX_CMP(1); }static void fx_cmp_r2() { FX_CMP(2); }static void fx_cmp_r3() { FX_CMP(3); }static void fx_cmp_r4() { FX_CMP(4); }static void fx_cmp_r5() { FX_CMP(5); }static void fx_cmp_r6() { FX_CMP(6); }static void fx_cmp_r7() { FX_CMP(7); }static void fx_cmp_r8() { FX_CMP(8); }static void fx_cmp_r9() { FX_CMP(9); }static void fx_cmp_r10() { FX_CMP(10); }static void fx_cmp_r11() { FX_CMP(11); }static void fx_cmp_r12() { FX_CMP(12); }static void fx_cmp_r13() { FX_CMP(13); }static void fx_cmp_r14() { FX_CMP(14); }static void fx_cmp_r15() { FX_CMP(15); }/* 70 - merge - R7 as upper byte, R8 as lower byte (used for texture-mapping) */static void fx_merge(){    uint32 v = (R7&0xff00) | ((R8&0xff00)>>8);    R15++; DREG = v;    GSU.vOverflow = (v & 0xc0c0) << 16;    GSU.vZero = !(v & 0xf0f0);    GSU.vSign = ((v | (v<<8)) & 0x8000);    GSU.vCarry = (v & 0xe0e0) != 0;    TESTR14;    CLRFLAGS;}/* 71-7f - and rn - reister & register */#define FX_AND(reg) \uint32 v = SREG & GSU.avReg[reg]; \R15++; DREG = v; \GSU.vSign = v; \GSU.vZero = v; \TESTR14; \CLRFLAGS;static void fx_and_r1() { FX_AND(1); }static void fx_and_r2() { FX_AND(2); }static void fx_and_r3() { FX_AND(3); }static void fx_and_r4() { FX_AND(4); }static void fx_and_r5() { FX_AND(5); }static void fx_and_r6() { FX_AND(6); }static void fx_and_r7() { FX_AND(7); }static void fx_and_r8() { FX_AND(8); }static void fx_and_r9() { FX_AND(9); }static void fx_and_r10() { FX_AND(10); }static void fx_and_r11() { FX_AND(11); }static void fx_and_r12() { FX_AND(12); }static void fx_and_r13() { FX_AND(13); }static void fx_and_r14() { FX_AND(14); }static void fx_and_r15() { FX_AND(15); }/* 71-7f(ALT1) - bic rn - reister & ~register */#define FX_BIC(reg) \uint32 v = SREG & ~GSU.avReg[reg];	\R15++; DREG = v; \GSU.vSign = v; \GSU.vZero = v; \TESTR14; \CLRFLAGS;static void fx_bic_r1() { FX_BIC(1); }static void fx_bic_r2() { FX_BIC(2); }static void fx_bic_r3() { FX_BIC(3); }static void fx_bic_r4() { FX_BIC(4); }static void fx_bic_r5() { FX_BIC(5); }static void fx_bic_r6() { FX_BIC(6); }static void fx_bic_r7() { FX_BIC(7); }static void fx_bic_r8() { FX_BIC(8); }static void fx_bic_r9() { FX_BIC(9); }static void fx_bic_r10() { FX_BIC(10); }static void fx_bic_r11() { FX_BIC(11); }static void fx_bic_r12() { FX_BIC(12); }static void fx_bic_r13() { FX_BIC(13); }static void fx_bic_r14() { FX_BIC(14); }static void fx_bic_r15() { FX_BIC(15); }/* 71-7f(ALT2) - and #n - reister & immediate */#define FX_AND_I(imm) \uint32 v = SREG & imm; \R15++; DREG = v; \GSU.vSign = v; \GSU.vZero = v; \TESTR14; \CLRFLAGS;static void fx_and_i1() { FX_AND_I(1); }static void fx_and_i2() { FX_AND_I(2); }static void fx_and_i3() { FX_AND_I(3); }static void fx_and_i4() { FX_AND_I(4); }static void fx_and_i5() { FX_AND_I(5); }static void fx_and_i6() { FX_AND_I(6); }static void fx_and_i7() { FX_AND_I(7); }static void fx_and_i8() { FX_AND_I(8); }static void fx_and_i9() { FX_AND_I(9); }static void fx_and_i10() { FX_AND_I(10); }static void fx_and_i11() { FX_AND_I(11); }static void fx_and_i12() { FX_AND_I(12); }static void fx_and_i13() { FX_AND_I(13); }static void fx_and_i14() { FX_AND_I(14); }static void fx_and_i15() { FX_AND_I(15); }/* 71-7f(ALT3) - bic #n - reister & ~immediate */#define FX_BIC_I(imm) \uint32 v = SREG & ~imm; \R15++; DREG = v; \GSU.vSign = v; \GSU.vZero = v; \TESTR14; \CLRFLAGS;static void fx_bic_i1() { FX_BIC_I(1); }static void fx_bic_i2() { FX_BIC_I(2); }static void fx_bic_i3() { FX_BIC_I(3); }static void fx_bic_i4() { FX_BIC_I(4); }static void fx_bic_i5() { FX_BIC_I(5); }static void fx_bic_i6() { FX_BIC_I(6); }static void fx_bic_i7() { FX_BIC_I(7); }static void fx_bic_i8() { FX_BIC_I(8); }static void fx_bic_i9() { FX_BIC_I(9); }static void fx_bic_i10() { FX_BIC_I(10); }static void fx_bic_i11() { FX_BIC_I(11); }static void fx_bic_i12() { FX_BIC_I(12); }static void fx_bic_i13() { FX_BIC_I(13); }static void fx_bic_i14() { FX_BIC_I(14); }static void fx_bic_i15() { FX_BIC_I(15); }/* 80-8f - mult rn - 8 bit to 16 bit signed multiply, register * register */#define FX_MULT(reg) \uint32 v = (uint32)(SEX8(SREG) * SEX8(GSU.avReg[reg])); \R15++; DREG = v; \GSU.vSign = v; \GSU.vZero = v; \TESTR14; \CLRFLAGS;static void fx_mult_r0() { FX_MULT(0); }static void fx_mult_r1() { FX_MULT(1); }static void fx_mult_r2() { FX_MULT(2); }static void fx_mult_r3() { FX_MULT(3); }static void fx_mult_r4() { FX_MULT(4); }static void fx_mult_r5() { FX_MULT(5); }static void fx_mult_r6() { FX_MULT(6); }static void fx_mult_r7() { FX_MULT(7); }static void fx_mult_r8() { FX_MULT(8); }static void fx_mult_r9() { FX_MULT(9); }static void fx_mult_r10() { FX_MULT(10); }static void fx_mult_r11() { FX_MULT(11); }static void fx_mult_r12() { FX_MULT(12); }static void fx_mult_r13() { FX_MULT(13); }static void fx_mult_r14() { FX_MULT(14); }static void fx_mult_r15() { FX_MULT(15); }/* 80-8f(ALT1) - umult rn - 8 bit to 16 bit unsigned multiply, register * register */#define FX_UMULT(reg) \uint32 v = USEX8(SREG) * USEX8(GSU.avReg[reg]); \R15++; DREG = v; \GSU.vSign = v; \GSU.vZero = v; \TESTR14; \CLRFLAGS;static void fx_umult_r0() { FX_UMULT(0); }static void fx_umult_r1() { FX_UMULT(1); }static void fx_umult_r2() { FX_UMULT(2); }static void fx_umult_r3() { FX_UMULT(3); }static void fx_umult_r4() { FX_UMULT(4); }static void fx_umult_r5() { FX_UMULT(5); }static void fx_umult_r6() { FX_UMULT(6); }static void fx_umult_r7() { FX_UMULT(7); }static void fx_umult_r8() { FX_UMULT(8); }static void fx_umult_r9() { FX_UMULT(9); }static void fx_umult_r10() { FX_UMULT(10); }static void fx_umult_r11() { FX_UMULT(11); }static void fx_umult_r12() { FX_UMULT(12); }static void fx_umult_r13() { FX_UMULT(13); }static void fx_umult_r14() { FX_UMULT(14); }static void fx_umult_r15() { FX_UMULT(15); }  /* 80-8f(ALT2) - mult #n - 8 bit to 16 bit signed multiply, register * immediate */#define FX_MULT_I(imm) \uint32 v = (uint32) (SEX8(SREG) * ((int32)imm)); \R15++; DREG = v; \GSU.vSign = v; \GSU.vZero = v; \TESTR14; \CLRFLAGS;static void fx_mult_i0() { FX_MULT_I(0); }static void fx_mult_i1() { FX_MULT_I(1); }static void fx_mult_i2() { FX_MULT_I(2); }static void fx_mult_i3() { FX_MULT_I(3); }static void fx_mult_i4() { FX_MULT_I(4); }static void fx_mult_i5() { FX_MULT_I(5); }static void fx_mult_i6() { FX_MULT_I(6); }static void fx_mult_i7() { FX_MULT_I(7); }static void fx_mult_i8() { FX_MULT_I(8); }static void fx_mult_i9() { FX_MULT_I(9); }static void fx_mult_i10() { FX_MULT_I(10); }static void fx_mult_i11() { FX_MULT_I(11); }static void fx_mult_i12() { FX_MULT_I(12); }static void fx_mult_i13() { FX_MULT_I(13); }static void fx_mult_i14() { FX_MULT_I(14); }static void fx_mult_i15() { FX_MULT_I(15); }  /* 80-8f(ALT3) - umult #n - 8 bit to 16 bit unsigned multiply, register * immediate */#define FX_UMULT_I(imm) \uint32 v = USEX8(SREG) * ((uint32)imm); \R15++; DREG = v; \GSU.vSign = v; \GSU.vZero = v; \TESTR14; \CLRFLAGS;static void fx_umult_i0() { FX_UMULT_I(0); }static void fx_umult_i1() { FX_UMULT_I(1); }static void fx_umult_i2() { FX_UMULT_I(2); }static void fx_umult_i3() { FX_UMULT_I(3); }static void fx_umult_i4() { FX_UMULT_I(4); }static void fx_umult_i5() { FX_UMULT_I(5); }static void fx_umult_i6() { FX_UMULT_I(6); }static void fx_umult_i7() { FX_UMULT_I(7); }static void fx_umult_i8() { FX_UMULT_I(8); }static void fx_umult_i9() { FX_UMULT_I(9); }static void fx_umult_i10() { FX_UMULT_I(10); }static void fx_umult_i11() { FX_UMULT_I(11); }static void fx_umult_i12() { FX_UMULT_I(12); }static void fx_umult_i13() { FX_UMULT_I(13); }static void fx_umult_i14() { FX_UMULT_I(14); }static void fx_umult_i15() { FX_UMULT_I(15); }  /* 90 - sbk - store word to last accessed RAM address */static void fx_sbk(){    RAM(GSU.vLastRamAdr) = (uint8)SREG;    RAM(GSU.vLastRamAdr^1) = (uint8)(SREG>>8);    CLRFLAGS;    R15++;}/* 91-94 - link #n - R11 = R15 + immediate */#define FX_LINK_I(lkn) R11 = R15 + lkn; CLRFLAGS; R15++static void fx_link_i1() { FX_LINK_I(1); }static void fx_link_i2() { FX_LINK_I(2); }static void fx_link_i3() { FX_LINK_I(3); }static void fx_link_i4() { FX_LINK_I(4); }/* 95 - sex - sign extend 8 bit to 16 bit */static void fx_sex(){    uint32 v = (uint32)SEX8(SREG);    R15++; DREG = v;    GSU.vSign = v;    GSU.vZero = v;    TESTR14;    CLRFLAGS;}/* 96 - asr - aritmetric shift right by one */static void fx_asr(){    uint32 v;    GSU.vCarry = SREG & 1;    v = (uint32)(SEX16(SREG)>>1);    R15++; DREG = v;    GSU.vSign = v;    GSU.vZero = v;    TESTR14;    CLRFLAGS;}/* 96(ALT1) - div2 - aritmetric shift right by one */static void fx_div2(){    uint32 v;    int32 s = SEX16(SREG);    GSU.vCarry = s & 1;    if(s == -1)	v = 0;    else	v = (uint32)(s>>1);    R15++; DREG = v;    GSU.vSign = v;    GSU.vZero = v;    TESTR14;    CLRFLAGS;}/* 97 - ror - rotate right by one */static void fx_ror(){    uint32 v = (USEX16(SREG)>>1) | (GSU.vCarry<<15);    GSU.vCarry = SREG & 1;    R15++; DREG = v;    GSU.vSign = v;    GSU.vZero = v;    TESTR14;    CLRFLAGS;}/* 98-9d - jmp rn - jump to address of register */#define FX_JMP(reg) \R15 = GSU.avReg[reg]; \CLRFLAGS;static void fx_jmp_r8() { FX_JMP(8); }static void fx_jmp_r9() { FX_JMP(9); }static void fx_jmp_r10() { FX_JMP(10); }static void fx_jmp_r11() { FX_JMP(11); }static void fx_jmp_r12() { FX_JMP(12); }static void fx_jmp_r13() { FX_JMP(13); }/* 98-9d(ALT1) - ljmp rn - set program bank to source register and jump to address of register */#define FX_LJMP(reg) \GSU.vPrgBankReg = GSU.avReg[reg] & 0x7f; \GSU.pvPrgBank = GSU.apvRomBank[GSU.vPrgBankReg]; \R15 = SREG; \
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