📄 memmap.cpp
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BlockIsROM [i] = BlockIsROM [i + 0x800] = TRUE; } } for(c=0;c<8;c++) { Map[(c<<4)+0x105]=(uint8*)MAP_LOROM_SRAM; BlockIsROM [(c<<4)+0x105] = FALSE; BlockIsRAM [(c<<4)+0x105] = TRUE; } /* // Banks 40->7f and c0->ff for (c = 0; c < 0x400; c += 16) { for (i = c; i < c + 8; i++) Map [i + 0x400] = Map [i + 0xc00] = &ROM [(c << 11) % CalculatedSize]; for (i = c + 8; i < c + 16; i++) Map [i + 0x400] = Map [i + 0xc00] = &ROM [((c << 11) + 0x200000) % CalculatedSize - 0x8000]; for (i = c; i < c + 16; i++) { BlockIsROM [i + 0x400] = BlockIsROM [i + 0xc00] = TRUE; } } */ for(c=1;c<=4;c++) { for(i=0;i<16; i++) { Map[0x400+i+(c<<4)]=(uint8*)MAP_LOROM_SRAM; BlockIsRAM[0x400+i+(c<<4)]=TRUE; BlockIsROM[0x400+i+(c<<4)]=FALSE; } } for(i=0;i<0x80;i++) { Map[0x700+i]=&BSRAM[0x10000*(i/16)]; BlockIsRAM[0x700+i]=TRUE; BlockIsROM[0x700+i]=FALSE; } for (i=0; i<8;i++) { Map[0x205+(i<<4)]=Map[0x285+(i<<4)]=Map[0x305+(i<<4)]=Map[0x385+(i<<4)]=Map[0x705+(i<<4)]; BlockIsRAM[0x205+(i<<4)]=BlockIsRAM[0x285+(i<<4)]=BlockIsRAM[0x305+(i<<4)]=BlockIsRAM[0x385+(i<<4)]=TRUE; BlockIsROM[0x205+(i<<4)]=BlockIsROM[0x285+(i<<4)]=BlockIsROM[0x305+(i<<4)]=BlockIsROM[0x385+(i<<4)]=FALSE; } for(c=0;c<8;c++) { Map[(c<<4)+0x005]=BSRAM-0x5000; BlockIsROM [(c<<4)+0x005] = FALSE; BlockIsRAM [(c<<4)+0x005] = TRUE; } MapRAM (); WriteProtectROM ();}void CMemory::HiROMMap (){ int i; int c; int j; int mask[4]; for (j=0; j<4; j++) mask[j]=0x00ff; mask[0]=(CalculatedSize/0x10000)-1; if (Settings.ForceSA1 || (!Settings.ForceNoSA1 && (ROMSpeed & ~0x10) == 0x23 && (ROMType & 0xf) > 3 && (ROMType & 0xf0) == 0x30)) { Settings.DisplayColor=BUILD_PIXEL(31,0,0); SET_UI_COLOR(255,0,0); } int x; bool foundZeros; bool pastZeros; for(j=0;j<3;j++) { x=1; foundZeros=false; pastZeros=false; mask[j+1]=mask[j]; while (x>0x100&&!pastZeros) { if(mask[j]&x) { x<<=1; if(foundZeros) pastZeros=true; } else { foundZeros=true; pastZeros=false; mask[j+1]|=x; x<<=1; } } } // Banks 00->3f and 80->bf for (c = 0; c < 0x400; c += 16) { Map [c + 0] = Map [c + 0x800] = RAM; BlockIsRAM [c + 0] = BlockIsRAM [c + 0x800] = TRUE; Map [c + 1] = Map [c + 0x801] = RAM; BlockIsRAM [c + 1] = BlockIsRAM [c + 0x801] = TRUE; Map [c + 2] = Map [c + 0x802] = (uint8 *) MAP_PPU; Map [c + 3] = Map [c + 0x803] = (uint8 *) MAP_PPU; Map [c + 4] = Map [c + 0x804] = (uint8 *) MAP_CPU; Map [c + 5] = Map [c + 0x805] = (uint8 *) MAP_CPU; if (Settings.DSP1Master) { Map [c + 6] = Map [c + 0x806] = (uint8 *) MAP_DSP; Map [c + 7] = Map [c + 0x807] = (uint8 *) MAP_DSP; } else { Map [c + 6] = Map [c + 0x806] = (uint8 *) MAP_NONE; Map [c + 7] = Map [c + 0x807] = (uint8 *) MAP_NONE; } for (i = c + 8; i < c + 16; i++) { int e=3; int d=c>>4; while(d>mask[0]) { d&=mask[e]; e--; } Map [i] = Map [i + 0x800] = ROM + (d*0x10000); BlockIsROM [i] = BlockIsROM [i + 0x800] = TRUE; } } // Banks 30->3f and b0->bf, address ranges 6000->7fff is S-RAM. for (c = 0; c < 16; c++) { Map [0x306 + (c << 4)] = (uint8 *) MAP_HIROM_SRAM; Map [0x307 + (c << 4)] = (uint8 *) MAP_HIROM_SRAM; Map [0xb06 + (c << 4)] = (uint8 *) MAP_HIROM_SRAM; Map [0xb07 + (c << 4)] = (uint8 *) MAP_HIROM_SRAM; BlockIsRAM [0x306 + (c << 4)] = TRUE; BlockIsRAM [0x307 + (c << 4)] = TRUE; BlockIsRAM [0xb06 + (c << 4)] = TRUE; BlockIsRAM [0xb07 + (c << 4)] = TRUE; } // Banks 40->7f and c0->ff for (c = 0; c < 0x400; c += 16) { for (i = c; i < c + 16; i++) { int e=3; int d=(c)>>4; while(d>mask[0]) { d&=mask[e]; e--; } Map [i + 0x400] = Map [i + 0xc00] = ROM + (d*0x10000); BlockIsROM [i + 0x400] = BlockIsROM [i + 0xc00] = TRUE; } } int bankmax=0x40+ (1<<(ROMSize-6)); //safety for corrupt headers if(bankmax > 128) bankmax = 0x80; int sum=0; for(i=0x40;i<bankmax; i++) { uint8 * bank_low=(uint8*)Map[i<<4]; for (c=0;c<0x10000; c++) { sum+=bank_low[c]; } } CalculatedChecksum=sum&0xFFFF; MapRAM (); WriteProtectROM ();}void CMemory::TalesROMMap (bool8 Interleaved){ int c; int i; if(Interleaved) { if(Settings.DisplayColor==0xffff) { Settings.DisplayColor=BUILD_PIXEL(0,31,0); SET_UI_COLOR(0,255,0); } } uint32 OFFSET0 = 0x400000; uint32 OFFSET1 = 0x400000; uint32 OFFSET2 = 0x000000; if (Interleaved) { OFFSET0 = 0x000000; OFFSET1 = 0x000000; OFFSET2 = CalculatedSize-0x400000; //changed to work with interleaved DKJM2. } // Banks 00->3f and 80->bf for (c = 0; c < 0x400; c += 16) { Map [c + 0] = Map [c + 0x800] = RAM; Map [c + 1] = Map [c + 0x801] = RAM; BlockIsRAM [c + 0] = BlockIsRAM [c + 0x800] = TRUE; BlockIsRAM [c + 1] = BlockIsRAM [c + 0x801] = TRUE; Map [c + 2] = Map [c + 0x802] = (uint8 *) MAP_PPU; Map [c + 3] = Map [c + 0x803] = (uint8 *) MAP_PPU; Map [c + 4] = Map [c + 0x804] = (uint8 *) MAP_CPU; Map [c + 5] = Map [c + 0x805] = (uint8 *) MAP_CPU; //makes more sense to map the range here. //ToP seems to use sram to skip intro??? if(c>=0x300) { Map [c + 6] = Map [c + 0x806] = (uint8 *) MAP_HIROM_SRAM; Map [c + 7] = Map [c + 0x807] = (uint8 *) MAP_HIROM_SRAM; BlockIsRAM [6 + c] = BlockIsRAM [7 + c] = BlockIsRAM [0x806 + c]= BlockIsRAM [0x807 + c] = TRUE; } else { Map [c + 6] = Map [c + 0x806] = (uint8 *) MAP_NONE; Map [c + 7] = Map [c + 0x807] = (uint8 *) MAP_NONE; } for (i = c + 8; i < c + 16; i++) { Map [i] = &ROM [((c << 12) % (CalculatedSize-0x400000)) + OFFSET0]; Map [i + 0x800] = &ROM [((c << 12) % 0x400000) + OFFSET2]; BlockIsROM [i] = TRUE; BlockIsROM [i + 0x800] = TRUE; } } // Banks 40->7f and c0->ff for (c = 0; c < 0x400; c += 16) { for (i = c; i < c + 8; i++) { Map [i + 0x400] = &ROM [((c << 12) % (CalculatedSize-0x400000)) + OFFSET1]; Map [i + 0x408] = &ROM [((c << 12) % (CalculatedSize-0x400000)) + OFFSET1]; Map [i + 0xc00] = &ROM [((c << 12) %0x400000)+ OFFSET2]; Map [i + 0xc08] = &ROM [((c << 12) % 0x400000) + OFFSET2]; BlockIsROM [i + 0x400] = TRUE; BlockIsROM [i + 0x408] = TRUE; BlockIsROM [i + 0xc00] = TRUE; BlockIsROM [i + 0xc08] = TRUE; } } if((strncmp("TALES",(char*)Map[8]+0xFFC0, 5)==0)) { if(((*(Map[8]+0xFFDE))==(*(Map[0x808]+0xFFDE)))) { Settings.DisplayColor=BUILD_PIXEL(31,0,0); SET_UI_COLOR(255,0,0); } } ROMChecksum = *(Map[8]+0xFFDE) + (*(Map[8]+0xFFDF) << 8); ROMComplementChecksum = *(Map[8]+0xFFDC) + (*(Map[8]+0xFFDD) << 8);int sum=0;for(i=0x40;i<0x80; i++){ uint8 * bank_low=(uint8*)Map[i<<4]; uint8 * bank_high=(uint8*)Map[(i<<4)+0x800]; for (c=0;c<0x10000; c++) { sum+=bank_low[c]; sum+=bank_high[c]; }}CalculatedChecksum=sum&0xFFFF; MapRAM (); WriteProtectROM ();}void CMemory::AlphaROMMap (){ int c; int i; // Banks 00->3f and 80->bf for (c = 0; c < 0x400; c += 16) { Map [c + 0] = Map [c + 0x800] = RAM; Map [c + 1] = Map [c + 0x801] = RAM; BlockIsRAM [c + 0] = BlockIsRAM [c + 0x800] = TRUE; BlockIsRAM [c + 1] = BlockIsRAM [c + 0x801] = TRUE; Map [c + 2] = Map [c + 0x802] = (uint8 *) MAP_PPU; Map [c + 3] = Map [c + 0x803] = (uint8 *) MAP_PPU; Map [c + 4] = Map [c + 0x804] = (uint8 *) MAP_CPU; Map [c + 5] = Map [c + 0x805] = (uint8 *) MAP_CPU; Map [c + 6] = Map [c + 0x806] = (uint8 *) MAP_NONE; Map [c + 7] = Map [c + 0x807] = (uint8 *) MAP_NONE; for (i = c + 8; i < c + 16; i++) { Map [i] = Map [i + 0x800] = &ROM [c << 11] - 0x8000; BlockIsROM [i] = TRUE; } } // Banks 40->7f and c0->ff for (c = 0; c < 0x400; c += 16) { for (i = c; i < c + 16; i++) { Map [i + 0x400] = &ROM [(c << 12) % CalculatedSize]; Map [i + 0xc00] = &ROM [(c << 12) % CalculatedSize]; BlockIsROM [i + 0x400] = BlockIsROM [i + 0xc00] = TRUE; } } MapRAM (); WriteProtectROM ();}void DetectSuperFxRamSize(){ if(ROM[0x7FDA]==0x33) { Memory.SRAMSize=ROM[0x7FBD]; } else { if(strncmp(Memory.ROMName, "STAR FOX 2", 10)==0) { Memory.SRAMSize=6; } else Memory.SRAMSize=5; }}void CMemory::SuperFXROMMap (){ int c; int i; DetectSuperFxRamSize(); // Banks 00->3f and 80->bf for (c = 0; c < 0x400; c += 16) { Map [c + 0] = Map [c + 0x800] = RAM; Map [c + 1] = Map [c + 0x801] = RAM; BlockIsRAM [c + 0] = BlockIsRAM [c + 0x800] = TRUE; BlockIsRAM [c + 1] = BlockIsRAM [c + 0x801] = TRUE; Map [c + 2] = Map [c + 0x802] = (uint8 *) MAP_PPU; Map [c + 3] = Map [c + 0x803] = (uint8 *) MAP_PPU; Map [c + 4] = Map [c + 0x804] = (uint8 *) MAP_CPU; Map [c + 5] = Map [c + 0x805] = (uint8 *) MAP_CPU; Map [0x006 + c] = Map [0x806 + c] = (uint8 *) ::SRAM - 0x6000; Map [0x007 + c] = Map [0x807 + c] = (uint8 *) ::SRAM - 0x6000; BlockIsRAM [0x006 + c] = BlockIsRAM [0x007 + c] = BlockIsRAM [0x806 + c] = BlockIsRAM [0x807 + c] = TRUE; for (i = c + 8; i < c + 16; i++) { Map [i] = Map [i + 0x800] = &ROM [c << 11] - 0x8000; BlockIsROM [i] = BlockIsROM [i + 0x800] = TRUE; } } // Banks 40->7f and c0->ff for (c = 0; c < 0x400; c += 16) { for (i = c; i < c + 16; i++) { Map [i + 0x400] = Map [i + 0xc00] = &ROM [(c << 12) % CalculatedSize]; BlockIsROM [i + 0x400] = BlockIsROM [i + 0xc00] = TRUE; } } // Banks 7e->7f, RAM for (c = 0; c < 16; c++) { Map [c + 0x7e0] = RAM; Map [c + 0x7f0] = RAM + 0x10000; BlockIsRAM [c + 0x7e0] = TRUE; BlockIsRAM [c + 0x7f0] = TRUE; BlockIsROM [c + 0x7e0] = FALSE; BlockIsROM [c + 0x7f0] = FALSE; } // Banks 70->71, S-RAM for (c = 0; c < 32; c++) { Map [c + 0x700] = ::SRAM + (((c >> 4) & 1) << 16); BlockIsRAM [c + 0x700] = TRUE; BlockIsROM [c + 0x700] = FALSE; } // Replicate the first 2Mb of the ROM at ROM + 2MB such that each 32K // block is repeated twice in each 64K block. for (c = 0; c < 64; c++) { memmove (&ROM [0x200000 + c * 0x10000], &ROM [c * 0x8000], 0x8000); memmove (&ROM [0x208000 + c * 0x10000], &ROM [c * 0x8000], 0x8000); } WriteProtectROM ();}void CMemory::SA1ROMMap (){ int c; int i; // Banks 00->3f and 80->bf for (c = 0; c < 0x400; c += 16) { Map [c + 0] = Map [c + 0x800] = RAM; Map [c + 1] = Map [c + 0x801] = RAM; BlockIsRAM [c + 0] = BlockIsRAM [c + 0x800] = TRUE; BlockIsRAM [c + 1] = BlockIsRAM [c + 0x801] = TRUE; Map [c + 2] = Map [c + 0x802] = (uint8 *) MAP_PPU; Map [c + 3] = Map [c + 0x803] = (uint8 *) &Memory.FillRAM [0x3000] - 0x3000; Map [c + 4] = Map [c + 0x804] = (uint8 *) MAP_CPU; Map [c + 5] = Map [c + 0x805] = (uint8 *) MAP_CPU; Map [c + 6] = Map [c + 0x806] = (uint8 *) MAP_BWRAM; Map [c + 7] = Map [c + 0x807] = (uint8 *) MAP_BWRAM; for (i = c + 8; i < c + 16; i++) { Map [i] = Map [i + 0x800] = &ROM [c << 11] - 0x8000; BlockIsROM [i] = BlockIsROM [i + 0x800] = TRUE; } } // Banks 40->7f for (c = 0; c < 0x400; c += 16) { for (i = c; i < c + 16; i++) Map [i + 0x400] = (uint8 *) &SRAM [(c << 12) & 0x1ffff]; for (i = c; i < c + 16; i++) { BlockIsROM [i + 0x400] = FALSE; } } // c0->ff for (c = 0; c < 0x400; c += 16) { for (i = c; i < c + 16; i++) { Map [i + 0xc00] = &ROM [(c << 12) % CalculatedSize]; BlockIsROM [i + 0xc00] = TRUE; } } for (c = 0; c < 16; c++) { Map [c + 0x7e0] = RAM; Map [c + 0x7f0] = RAM + 0x10000; BlockIsRAM [c + 0x7e0] = TRUE; BlockIsRAM [c + 0x7f0] = TRUE; BlockIsROM [c + 0x7e0] = FALSE; BlockIsROM [c + 0x7f0] = FALSE; } WriteProtectROM (); // Now copy the map and correct it for the SA1 CPU. memmove ((void *) SA1.WriteMap, (void *) WriteMap, sizeof (WriteMap)); memmove ((void *) SA1.Map, (void *) Map, sizeof (Map)); // Banks 00->3f and 80->bf for (c = 0; c < 0x400; c += 16) { SA1.Map [c + 0] = SA1.Map [c + 0x800] = &Memory.FillRAM [0x3000]; SA1.Map [c + 1] = SA1.Map [c + 0x801] = (uint8 *) MAP_NONE; SA1.WriteMap [c + 0] = SA1.WriteMap [c + 0x800] = &Memory.FillRAM [0x3000]; SA1.WriteMap [c + 1] = SA1.WriteMap [c + 0x801] = (uint8 *) MAP_NONE; } // Banks 60->6f for (c = 0; c < 0x100; c++) SA1.Map [c + 0x600] = SA1.WriteMap [c + 0x600] = (uint8 *) MAP_BWRAM_BITMAP; BWRAM = SRAM;}void CMemory::LoROM24MBSMap (){ int c; int i; // Banks 00->3f and 80->bf for (c = 0; c < 0x400; c += 16) { Map [c + 0] = Map [c + 0x800] = RAM; Map [c + 1] = Map [c + 0x801] = RAM; BlockIsRAM [c + 0] = BlockIsRAM [c + 0x800] = TRUE; BlockIsRAM [c + 1] = BlockIsRAM [c + 0x801] = TRUE; Map [c + 2] = Map [c + 0x802] = (uint8 *) MAP_PPU; Map [c + 3] = Map [c + 0x803] = (uint8 *) MAP_PPU; Map [c + 4] = Map [c + 0x804] = (uint8 *) MAP_CPU; Map [c + 5] = Map [c + 0x805] = (uint8 *) MAP_CPU; Map [c + 6] = Map [c + 0x806] = (uint8 *) MAP_NONE; Map [c + 7] = Map [c + 0x807] = (uint8 *) MAP_NONE; for (i = c + 8; i < c + 16; i++) { Map [i] = Map [i + 0x800] = &ROM [c << 11] - 0x8000; BlockIsROM [i] = BlockIsROM [i + 0x8
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