getset.s

SFC游戏模拟器 snes9x 1.43 的原代码

	cmpl $0, SA1Opcodes
	movl $0, SA1WaitCounter
	setnz %al
	movb %al, SA1Executing
.NoMatch:
	popl %ecx
	movb %cl, (%edx)
#else
	popl %ecx
	movb %cl, (%eax, %edx)
#endif
	ret

.SBSpecial:
	jmp *.SBJmpTable(, %eax, 4)
.data
	.align 4
.SBJmpTable:
	.long .SBPPU    /* MAP_PPU */
	.long .SBCPU    /* MAP_CPU */
	.long .SBDSP    /* MAP_DSP */
	.long .SBLSRAM  /* MAP_LOROM_SRAM */
	.long .SBHSRAM  /* MAP_HIROM_SRAM */
	.long .SBNONE   /* MAP_NONE */
	.long .SBDEBUG  /* MAP_DEBUG */
	.long .SBC4     /* MAP_C4 */
	.long .SBBWRAM  /* MAP_BWRAM */
	.long .SBNONE   /* MAP_BWRAM_BITMAP */
	.long .SBNONE   /* MAP_BWRAM_BITMAP2 */
	.long .SBNONE   /* MAP_SA1RAM */
	.long .SBNONE   /* MAP_SPC7110_ROM */
	.long .SBNONE   /* MAP_SPC7110_DRAM */
	.long .SBNONE   /* MAP_RONLY_SRAM */
	.long .SBOBC1   /* MAP_OBC_RAM */
	.long .SBSDSP   /* MAP_SETA_DSP */
	.long .SBSRISC  /* MAP_SETA_RISC */

.text
.SBPPU: /* MAP_PPU */
	STORE_REGISTERS
	popl %eax
	pushl %edx	/* Save Address because S9xSetPPU can stomp it with certain optimizations enabled */
	pushl %edx
	pushl %eax
	ccall S9xSetPPU
	LOAD_REGISTERS
	addl $8, %esp
	popl %edx
	ret

.SBCPU: /* MAP_CPU */
	STORE_REGISTERS
	popl %eax
	pushl %edx
	pushl %eax
	ccall S9xSetCPU
	LOAD_REGISTERS
	addl $8, %esp
	ret

.SBDSP: /* MAP_DSP */
	popl %eax
	pushl %edx
	pushl %eax
	ccall S9xSetDSP
	LOAD_CYCLES
	addl $8, %esp
	ret

.SBLSRAM: /* MAP_LOROM_SRAM */
	popl %eax
	movl SRAMMask, %ecx
	orl %ecx, %ecx
	jz .SBLSRAM_SKIP
	movl %edx, %ecx
	andl $0x7fff, %edx
	andl $0x00ff0000, %ecx
	sarl $1, %ecx
	orl  %ecx, %edx
	movl SRAM, %ecx
	andl SRAMMask, %edx
	movb %al, (%ecx, %edx)
	movb $1, SRAMModified
.SBLSRAM_SKIP:
	ret

.SBHSRAM: /* MAP_HIROM_SRAM */
	popl %eax
	movl %edx, %ecx
	andl $0xf0000, %ecx
	andl $0x7fff, %edx
	sarl $3, %ecx
	addl $-24576, %edx
	addl %ecx, %edx
	movl SRAMMask, %ecx
	orl %ecx, %ecx
	jz .SBHSRAM_SKIP
	andl %ecx, %edx
	movl SRAM, %ecx
	movb %al, (%ecx, %edx)
	movb $1, SRAMModified
.SBHSRAM_SKIP:
	ret

.SBNONE:  /* MAP_NONE */
.SBDEBUG: /* MAP_DEBUG */
	popl %eax
	ret

.SBC4: /* MAP_C4 */
	STORE_REGISTERS
	popl %eax
	pushl %edx
	pushl %eax
	ccall S9xSetC4
	LOAD_REGISTERS
	addl $8, %esp
	ret

.SBBWRAM: /* MAP_BWRAM */
	andl $0x7fff, %edx
	popl %eax
	addl $-24576, %edx
	movl BWRAM, %ecx
	movb %al, (%ecx, %edx)
	movb $1, SRAMModified
	ret

.SBOBC1: /* MAP_OBC_RAM */
	STORE_REGISTERS
	popl %eax
	pushl %edx
	pushl %eax
	ccall SetOBC1
	LOAD_REGISTERS
	addl $8, %esp
	ret

.SBSDSP: /* MAP_SETA_DSP */
	STORE_REGISTERS
	popl %eax
	pushl %edx
	pushl %eax
	ccall S9xSetSetaDSP
	LOAD_REGISTERS
	addl $8, %esp
	ret

.SBSRISC: /* MAP_SETA_RISC */
	STORE_REGISTERS
	popl %eax
	pushl %edx
	pushl %eax
	ccall S9xSetST018
	LOAD_REGISTERS
	addl $8, %esp
	ret

.globl S9xSetWord

S9xSetWord:
	pushl %eax

	movl %edx, %eax
	andl $0x0fff, %eax
	cmpl $0x0fff, %eax
	jne .SWNotAtBlockBoundary
	xorl %eax, %eax
	pushl %edx
	movb 4(%esp), %al
	call S9xSetByte
	popl %edx
	xorl %eax, %eax
	incl %edx
	movb 1(%esp), %al
	call S9xSetByte
	popl %ecx
	ret

.SWNotAtBlockBoundary:

#ifdef CPU_SHUTDOWN
	movl $0, WaitAddress
#endif	
	movl %edx, %eax
	shrl $MEMMAP_SHIFT, %eax
	and $MEMMAP_MASK, %eax

	movb InDMA, %cl
	testb %cl, %cl
	jne .SW_NOADD
	movb MemorySpeed(%eax), %cl
	andl $0xff, %ecx
	addl %ecx, CYCLES
	addl %ecx, CYCLES
	SAVE_CYCLES
.SW_NOADD:
	movl WriteMap(, %eax, 4), %eax
	cmpl $18, %eax  /* MAP_LAST */
	jb .SWSpecial
	andl $0xffff, %edx
#ifdef CPU_SHUTDOWN
	addl %eax, %edx
	cmpl SA1WaitByteAddress1, %edx
	jz .Matched2
	cmpl SA1WaitByteAddress2, %edx
	jnz .NoMatch2
.Matched2:
	cmpl $0, SA1Opcodes
	movl $0, SA1WaitCounter
	setnz %al
	movb %al, SA1Executing
.NoMatch2:
	popl %ecx
	movw %cx, (%edx)
#else
	popl %ecx
	movw %cx, (%eax, %edx)
#endif
	ret

.SWSpecial:
	jmp *.SWJmpTable(, %eax, 4)
.data
	.align 4
.SWJmpTable:
	.long .SWPPU    /* MAP_PPU */
	.long .SWCPU    /* MAP_CPU */
	.long .SWDSP    /* MAP_DSP */
	.long .SWLSRAM  /* MAP_LOROM_SRAM */
	.long .SWHSRAM  /* MAP_HIROM_SRAM */
	.long .SWNONE   /* MAP_NONE */
	.long .SWDEBUG  /* MAP_DEBUG */
	.long .SWC4     /* MAP_C4 */
	.long .SWBWRAM  /* MAP_BWRAM */
	.long .SWNONE   /* MAP_BWRAM_BITMAP */
	.long .SWNONE   /* MAP_BWRAM_BITMAP2 */
	.long .SWNONE   /* MAP_SA1RAM */
	.long .SWNONE   /* MAP_SPC7110_ROM */
	.long .SWNONE   /* MAP_SPC7110_DRAM */
	.long .SWNONE   /* MAP_RONLY_SRAM */
	.long .SWOBC1   /* MAP_OBC_RAM */
	.long .SWSDSP   /* MAP_SETA_DSP */
	.long .SWSRISC  /* MAP_SETA_RISC */

.text
.SWPPU: /* MAP_PPU */
	STORE_REGISTERS
	popl %eax
	pushl %edx	/* Save Address because S9xSetPPU will use it with certain optimizations enabled */
	pushl %eax	/* Save Byte because S9xSetPPU will use it with certain optimizations enabled */
	pushl %edx
	pushl %eax
	ccall S9xSetPPU
	popl %eax
	popl %edx
	popl %eax
	popl %edx
	pushl %edx
	movb %ah, %al
	incl %edx
	pushl %edx
	pushl %eax
	ccall S9xSetPPU
	LOAD_REGISTERS
	addl $8, %esp
	popl %edx
	ret

.SWCPU: /* MAP_CPU */
	STORE_REGISTERS
	popl %eax
	pushl %edx
	pushl %eax
	ccall S9xSetCPU
	popl %eax
	popl %edx
	movb %ah, %al
	incl %edx
	pushl %edx
	pushl %eax
	ccall S9xSetCPU
	LOAD_REGISTERS
	addl $8, %esp
	ret

.SWDSP: /* MAP_DSP */
	popl %eax
	pushl %edx
	pushl %eax
	ccall S9xSetDSP
	popl %eax
	popl %edx
	movb %ah, %al
	incl %edx
	pushl %edx
	pushl %eax
	ccall S9xSetDSP
	LOAD_CYCLES
	addl $8, %esp
	ret

.SWLSRAM: /* MAP_LOROM_SRAM */
	popl %eax
	movl SRAMMask, %ecx
	orl %ecx, %ecx
	jz .SWLSRAM_SKIP
	movl %edx, %ecx
	andl $0x7fff, %edx
	andl $0x00ff0000, %ecx
	sarl $1, %ecx
	orl  %ecx, %edx
	movl SRAM, %ecx
	andl SRAMMask, %edx
	movb %al, (%ecx, %edx)
	incl %edx
	andl SRAMMask, %edx
	movb %ah, (%ecx, %edx)
	movb $1, SRAMModified
.SWLSRAM_SKIP:
	ret

.SWHSRAM: /* MAP_HIROM_SRAM */
	popl %eax
	movl %edx, %ecx
	andl $0xf0000, %ecx
	andl $0x7fff, %edx
	sarl $3, %ecx
	addl $-24576, %edx
	addl %ecx, %edx
	movl SRAMMask, %ecx
	orl %ecx, %ecx
	jz .SWHSRAM_SKIP
	andl %ecx, %edx
	movl SRAM, %ecx
	movb %al, (%ecx, %edx)
	incl %edx
	andl SRAMMask, %edx
	movb %ah, (%ecx, %edx)
	movb $1, SRAMModified
.SWHSRAM_SKIP:
	ret

.SWNONE:
.SWDEBUG: /* MAP_DEBUG */
	popl %eax
	ret

.SWC4: /* MAP_C4 */
	STORE_REGISTERS
	popl %eax
	pushl %edx
	pushl %eax
	ccall S9xSetC4
	popl %eax
	popl %edx
	movb %ah, %al
	incl %edx
	pushl %edx
	pushl %eax
	ccall S9xSetC4
	LOAD_REGISTERS
	addl $8, %esp
	ret

.SWBWRAM: /* MAP_BWRAM */
	andl $0x7fff, %edx
	popl %eax
	addl $-24576, %edx
	movl BWRAM, %ecx
	movw %ax, (%ecx, %edx)
	movb $1, SRAMModified
	ret

.SWOBC1: /* MAP_OBC1 */
	STORE_REGISTERS
	popl %eax
	pushl %edx
	pushl %eax
	ccall SetOBC1
	popl %eax
	popl %edx
	movb %ah, %al
	incl %edx
	pushl %edx
	pushl %eax
	ccall SetOBC1
	LOAD_REGISTERS
	addl $8, %esp
	ret

.SWSDSP: /* MAP_SETA_DSP */
	STORE_REGISTERS
	popl %eax
	pushl %edx
	pushl %eax
	ccall S9xSetSetaDSP
	popl %eax
	popl %edx
	movb %ah, %al
	incl %edx
	pushl %edx
	pushl %eax
	ccall S9xSetSetaDSP
	LOAD_REGISTERS
	addl $8, %esp
	ret

.SWSRISC: /* MAP_SETA_RISC */
	STORE_REGISTERS
	popl %eax
	pushl %edx
	pushl %eax
	ccall S9xSetST018
	popl %eax
	popl %edx
	movb %ah, %al
	incl %edx
	pushl %edx
	pushl %eax
	ccall S9xSetST018
	LOAD_REGISTERS
	addl $8, %esp
	ret


.globl S9xSetPCBase

S9xSetPCBase:
	movl %edx, %eax
	shrl $MEMMAP_SHIFT, %eax
	and $MEMMAP_MASK, %eax
	movb MemorySpeed(%eax), %cl
	andl $0xff, %ecx
	movl %ecx, MemSpeed
	addl %ecx, %ecx
	movl %ecx, MemSpeedx2
	movl Map(, %eax, 4), %eax
	cmpl $18, %eax  /* MAP_LAST */
	jb .SPCSpecial
	andl $0xffff, %edx
	movl %eax, PCBase
	addl %edx, %eax
	movl %eax, PC
	ret

	.align 4
.SPCSpecial:
	jmp *.SPCJmpTable(, %eax, 4)
.data
	.align 4
.SPCJmpTable:
	.long .SPCPPU    /* MAP_PPU */
	.long .SPCCPU    /* MAP_CPU */
	.long .SPCDSP    /* MAP_DSP */
	.long .SPCLSRAM  /* MAP_LOROM_SRAM */
	.long .SPCHSRAM  /* MAP_HIROM_SRAM */
	.long .SPCNONE   /* MAP_NONE */
	.long .SPCDEBUG  /* MAP_DEBUG */
	.long .SPCC4     /* MAP_C4 */
	.long .SPCBWRAM  /* MAP_BWRAM */
	.long .SPCNONE   /* MAP_BWRAM_BITMAP */
	.long .SPCNONE   /* MAP_BWRAM_BITMAP2 */
	.long .SPCNONE   /* MAP_SA1RAM */
	.long .SPCNONE   /* MAP_SPC7110_ROM */
	.long .SPCNONE   /* MAP_SPC7110_DRAM */
	.long .SPCNONE   /* MAP_RONLY_SRAM */
	.long .SPCNONE   /* MAP_OBC_RAM */
	.long .SPCNONE   /* MAP_SETA_DSP */
	.long .SPCNONE   /* MAP_SETA_RISC */

.text
.SPCPPU: /* MAP_PPU */
	movl FillRAM, %ecx
	andl $0xffff, %edx
	movl %ecx, PCBase
	addl %edx, %ecx
	movl %ecx, PC
	ret

.SPCCPU: /* MAP_CPU */
	movl FillRAM, %ecx
	andl $0xffff, %edx
	movl %ecx, PCBase
	addl %edx, %ecx
	movl %ecx, PC
	ret

.SPCDSP: /* MAP_DSP */
	movl FillRAM, %ecx
	andl $0xffff, %edx
	movl %ecx, PCBase
	addl %edx, %ecx
	movl %ecx, PC
	ret

.SPCLSRAM: /* MAP_LOROM_SRAM */
	movl SRAM, %ecx
	andl $0xffff, %edx
	movl %ecx, PCBase
	addl %edx, %ecx
	movl %ecx, PC
	ret

.SPCHSRAM: /* MAP_HIROM_SRAM */
	movl SRAM, %eax
	andl $0xffff, %edx
	addl $-24576, %eax
	movl %eax, PCBase
	addl %eax, %edx
	movl %edx, PC
	ret

.SPCNONE:
.SPCDEBUG: /* MAP_DEBUG */
	movl SRAM, %eax
	andl $0xffff, %edx
	movl %eax, PCBase
	addl %eax, %edx
	movl %edx, PC
	ret

.SPCC4: /* MAP_C4 */
	movl C4RAM, %ecx
	andl $0xffff, %edx
	addl $-0x6000, %ecx
	movl %ecx, PCBase
	addl %edx, %ecx
	movl %ecx, PC
	ret

.SPCBWRAM: /* MAP_BWRAM */
	movl SRAM, %eax
	andl $0xffff, %edx
	addl $-24576, %eax
	movl %eax, PCBase
	addl %eax, %edx
	movl %edx, PC
	ret