📄 cpuops.s
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#ifdef DEBUGGER .align 4.LC1: .ascii "*** IRQ" .byte 0#endif .align 4.FillRAM2: .long FillRAM.n2209: .word 0x2209 .globl S9xOpcode_NMI_rS9xOpcode_NMI_r:#if 0 PUSH_REGISTERS sts.l pr,@-r15 mova .foofoo,r0 mov.l @r0+,r1 jsr @r1 mov r0,r4 lds.l @r15+,pr POP_REGISTERS#endif#ifdef DEBUGGER testb $TRACE_FLAG, Flags je .NMI_NO_TRACE pushl $.LC2 ccall S9xTraceMessage addl $4, %esp.NMI_NO_TRACE:#endif mov.w .emflag2,r0 sts.l pr,@-r15 tst r0,FLAGS16 bf .NMI_EMULATION mov.b PB, r0 PushByte NMI1 mov.l PCBase,r0 neg r0,r0 add PC, r0 PushWord NMI2 S9xPackStatus NMI extu.b FLAGS, r0 mov #Decimal|IRQ,r1 or r1,FLAGS add #-Decimal, FLAGS PushByte NMI3 mov.l ICPU,r3 mov #0,r0 mov.l r0,@(16,r3) mov.b r0,PB#ifdef VAR_CYCLES add #12, CYCLES#else add #8, CYCLES#endif mov.l S9xGetWord,r3 mov #-0x16,r4 jsr @r3 extu.w r4,r4 mov.l S9xSetPCBase,r3 lds.l @r15+,pr jmp @r3 extu.w r0,r4.NMI_EMULATION: mov.l PCBase,r0 neg r0,r0 add PC, r0 PushWord NMI4 S9xPackStatus NMI2 extu.b FLAGS, r0 mov #Decimal|IRQ,r1 or r1,FLAGS add #-Decimal, FLAGS PushByte NMI5 mov.l ICPU,r3 mov #0,r0 mov.l r0,@(16,r3) mov.b r0,PB#ifdef VAR_CYCLES add #6, CYCLES#else add #6, CYCLES#endif mov.l S9xGetWord,r3 mov #-0x6,r4 jsr @r3 extu.w r4,r4 mov.l S9xSetPCBase,r3 lds.l @r15+,pr jmp @r3 extu.w r0,r4.emflag2: .word Emulation#ifdef DEBUGGER .align 4.LC2: .ascii "*** NMI" .byte 0#endif .align 2.foofoo: .long _reportf .ascii "[NMI]" .byte 10,0 .align 1 Op02:#ifdef DEBUGGER testb $TRACE_FLAG, Flags je .COP_NO_TRACE pushl $.LC3 ccall S9xTraceMessage addl $4,%esp.COP_NO_TRACE:#endif mov.w .emflag25,r0 tst r0,FLAGS16 bf .COP_EMULATION mov.b PB, r0 PushByte COP1 mov.l PCBase,r0 neg r0,r0 add PC, r0 add #1,r0 PushWord COP2 S9xPackStatus COP extu.b FLAGS, r0 mov #Decimal|IRQ,r1 or r1,FLAGS add #-Decimal, FLAGS PushByte COP3 mov.l ICPU,r3 mov #0,r0 mov.l r0,@(16,r3) mov.b r0,PB#ifdef VAR_CYCLES add #12, CYCLES#else add #8, CYCLES#endif mov.l S9xGetWord,r3 mov #-0x1c,r4 jsr @r3 extu.w r4,r4 mov.l S9xSetPCBase,r3 extu.w r0,r4 Xlink.COP_EMULATION: mov.l PCBase,r0 neg r0,r0 add PC, r0 add #1,r0 PushWord COP4 S9xPackStatus COP2 extu.b FLAGS, r0 mov #Decimal|IRQ,r1 or r1,FLAGS add #-Decimal, FLAGS PushByte COP5 mov.l ICPU,r3 mov #0,r0 mov.l r0,@(16,r3) mov.b r0,PB#ifdef VAR_CYCLES add #6, CYCLES#else add #6, CYCLES#endif mov.l S9xGetWord,r3 mov #-0xc,r4 jsr @r3 extu.w r4,r4 mov.l S9xSetPCBase,r3 extu.w r0,r4 Xlink.emflag25: .word Emulation #ifdef DEBUGGER .align 4.LC3: .ascii "*** COP" .byte 0#endif /* JML */OpDC: AbsoluteIndirectLong8 JML mov.l ICPU,r3 mov.l r0,@(16,r3) shlr16 r0 mov.l S9xSetPCBase,r3 mov.b r0,PB#ifdef VAR_CYCLES add #12, CYCLES#endif XlinkOp5C: AbsoluteLong8 JML mov.l ICPU,r3 mov.l r0,@(16,r3) shlr16 r0 mov.l S9xSetPCBase,r3 mov.b r0,PB Xlink/* JMP */Op4C: Absolute8 JMP mov.l ICPU,r3 extu.w r4,r4 mov.l @(16,r3),r0 mov.l S9xSetPCBase,r3 or r0,r4 XlinkOp6C: AbsoluteIndirect8 JMP mov.l ICPU,r3 extu.w r4,r4 mov.l @(16,r3),r0 mov.l S9xSetPCBase,r3 or r0,r4 XlinkOp7C: AbsoluteIndexedIndirect8 JMP#ifdef VAR_CYCLES add #6, CYCLES#endif mov.l ICPU,r3 extu.w r4,r4 mov.l @(16,r3),r0 mov.l S9xSetPCBase,r3 or r0,r4 Xlink/* JSL */Op22: mov.b PB, r0 PushByte JSL_ABSL mov.l PCBase,r0 neg r0,r0 add PC, r0 add #2,r0 PushWord JSL_ABSL AbsoluteLong8 JSL mov.l ICPU,r3 mov.l r0,@(16,r3) shlr16 r0 mov.l S9xSetPCBase,r3 mov.b r0,PB Xlink/* RTL */Op6B:#ifdef VAR_CYCLES add #12, CYCLES#endif PullWord RTL mov.l r0,@-r15 PullByte RTL mov.l @r15+,r4 mov.b r0, PB add #1,r4 shll16 r0 extu.w r4,r4 mov.l ICPU,r3 mov.l r0,@(16,r3) mov.l S9xSetPCBase,r3 or r0,r4 Xlink/* JSR ABS */Op20:#ifdef VAR_CYCLES add #6, CYCLES#endif mov.l PCBase,r0 neg r0,r0 add PC, r0 add #1,r0 PushWord JSR_ABS Absolute8 JSR_ABS mov.l ICPU,r3 extu.w r4,r4 mov.l @(16,r3),r0 mov.l S9xSetPCBase,r3 or r0,r4 Xlink/* JSR ABS INDEXED INDIRECT */OpFC:#ifdef VAR_CYCLES add #6, CYCLES#endif mov.l PCBase,r0 neg r0,r0 add PC, r0 add #1,r0 PushWord JSR_AII AbsoluteIndexedIndirect8 JSR mov.l ICPU,r3 extu.w r4,r4 mov.l @(16,r3),r0 mov.l S9xSetPCBase,r3 or r0,r4 Xlink/* RTS */Op60:#ifdef VAR_CYCLES add #6 * 3, CYCLES#endif PullWord RTS add #1,r0 mov.l ICPU,r3 extu.w r0,r4 mov.l @(16,r3),r0 mov.l S9xSetPCBase,r3 or r0,r4 Xlink/* MVN */Op54X1:#ifdef VAR_CYCLES mov.l MemSpeedx2,r2 add r2,CYCLES add #12,CYCLES#endif mov.b @PC+,r0 mov.b r0,DB extu.b r0,r0 mov.l ICPU,r1 shll16 r0 mov.l r0,ShiftedDB mov.l r0,@-r15 mov.b @PC+,r4 mov.l S9xGetByte,r3 extu.b r4,r4 mov.w XX,r0 shll16 r4 extu.w r0,r0 jsr @r3 add r0,r4 mov r0,r5 mov.w YY,r0 mov.l S9xSetByte,r3 mov.l @r15+,r4 extu.w r0,r1 mov r5,r0 jsr @r3 add r1,r4 mov.b XL,r0 add #1,r0 mov.b r0,XL mov.b YL,r0 add #1,r0 mov.b r0,YL add #-1,A cmp/pz A bf/s .MVN_EXIT8 extu.w A,A jmp @r13 add #-3,PC.MVN_EXIT8: jmp @r13 nopOp54X0:#ifdef VAR_CYCLES mov.l MemSpeedx2,r2 add r2,CYCLES add #12,CYCLES#endif mov.b @PC+,r0 mov.b r0,DB extu.b r0,r0 mov.l ICPU,r1 shll16 r0 mov.l r0,ShiftedDB mov.l r0,@-r15 mov.b @PC+,r4 mov.l S9xGetByte,r3 extu.b r4,r4 mov.w XX,r0 shll16 r4 extu.w r0,r1 add #1,r0 add r1,r4 jsr @r3 mov.w r0,XX mov r0,r5 mov.w YY,r0 mov.l S9xSetByte,r3 mov.l @r15+,r4 extu.w r0,r1 add #1,r0 add r1,r4 mov.w r0,YY jsr @r3 mov r5,r0 add #-1,A cmp/pz A bf/s .MVN_EXIT16 extu.w A,A jmp @r13 add #-3,PC.MVN_EXIT16: jmp @r13 nop/* MVP */Op44X1:#ifdef VAR_CYCLES mov.l MemSpeedx2,r2 add r2,CYCLES add #12,CYCLES#endif mov.b @PC+,r0 mov.b r0,DB extu.b r0,r0 mov.l ICPU,r1 shll16 r0 mov.l r0,ShiftedDB mov.l r0,@-r15 mov.b @PC+,r4 mov.l S9xGetByte,r3 extu.b r4,r4 mov.w XX,r0 shll16 r4 extu.w r0,r0 jsr @r3 add r0,r4 mov r0,r5 mov.w YY,r0 mov.l S9xSetByte,r3 mov.l @r15+,r4 extu.w r0,r1 mov r5,r0 jsr @r3 add r1,r4 mov.b XL,r0 add #-1,r0 mov.b r0,XL mov.b YL,r0 add #-1,r0 mov.b r0,YL add #-1,A cmp/pz A bf/s .MVP_EXIT8 extu.w A,A jmp @r13 add #-3,PC.MVP_EXIT8: jmp @r13 nopOp44X0:#ifdef VAR_CYCLES mov.l MemSpeedx2,r2 add r2,CYCLES add #12,CYCLES#endif mov.b @PC+,r0 mov.b r0,DB extu.b r0,r0 mov.l ICPU,r1 shll16 r0 mov.l r0,ShiftedDB mov.l r0,@-r15 mov.b @PC+,r4 mov.l S9xGetByte,r3 extu.b r4,r4 mov.w XX,r0 shll16 r4 extu.w r0,r1 add #-1,r0 add r1,r4 jsr @r3 mov.w r0,XX mov r0,r5 mov.w YY,r0 mov.l S9xSetByte,r3 mov.l @r15+,r4 extu.w r0,r1 add #-1,r0 add r1,r4 mov.w r0,YY jsr @r3 mov r5,r0 add #-1,A cmp/pz A bf/s .MVP_EXIT16 extu.w A,A jmp @r13 add #-3,PC.MVP_EXIT16: jmp @r13 nop/* REP */OpC2:#ifdef VAR_CYCLES mov.l MemSpeed,r2 add r2,CYCLES add #6,CYCLES#endif mov.b @PC+,r0 mov #Zero,r1 extu.b r0,r0 mov #-1,r2 and r0,r1 not r0,r0 or r1,r7 and r0,FLAGS extu.w r2,r2 exts.b r0,r1 mov.w .emflag3,r0 or r2,r1 tst r0,FLAGS16 bt/s .REP_NO_EMU and r1,r7 mov #(MemoryFlag | IndexFlag), r0 or r0, FLAGS .REP_NO_EMU: mov #IndexFlag,r0 tst r0,FLAGS bt .REP16 mov #0,r0 mov.b r0,XH mov.b r0,YH.REP16: S9xFixCycles REP CheckForIrqjmp REP /* Removed in 1.39. See asmops.h *//* SEP */OpE2:#ifdef VAR_CYCLES mov.l MemSpeed,r2 add r2,CYCLES add #6,CYCLES#endif mov.b @PC+,r0 mov #Zero,r1 extu.b r0,r0 and r0,r1 exts.b r0,r2 shll8 r1 or r0,FLAGS shlr2 r1 extu.w r2,r0 exts.b r1,r1 sub r0,r2 shlr16 r1 or r2,r7 mov.w .emflag3,r0 not r1,r1 tst r0,FLAGS16 bt/s .SEP_NO_EMU and r1,r7 mov #(MemoryFlag | IndexFlag), r0 or r0, FLAGS .SEP_NO_EMU: mov #IndexFlag,r0 tst r0,FLAGS bt .SEP16 mov #0,r0 mov.b r0,XH mov.b r0,YH.SEP16: S9xFixCycles SEP jmp @r13 nop/* XBA */OpEB:#ifdef VAR_CYCLES add #12, CYCLES#endif swap.b A,A SetZNjmp A/* RTI */Op40:#ifdef VAR_CYCLES add #12, CYCLES#endif PullByte RTI extu.b FLAGS,r1 add r0,FLAGS sub r1,FLAGS PullWord RTI mov.w .emflag3,r1 mov.l r0,@-r15 tst r1, FLAGS16 bf .RTI_EMU PullByte RTI2 bra .RTI_SKIP_EMU extu.b r0,r0.RTI_EMU: mov #(MemoryFlag | IndexFlag), r0 mov.l ICPU,r3 or r0,FLAGS /*XXX: HERE xorl %eax, %eax*/ mov.l @(16,r3),r0 shlr16 r0.RTI_SKIP_EMU: mov.b r0,PB mov.l @r15+,r4 shll16 r0 mov.l ICPU,r3 mov.l r0,@(16,r3) mov.l S9xSetPCBase,r3 jsr @r3 or r0,r4 mov #IndexFlag,r0 tst r0,FLAGS bt .RTI16 mov #0,r0 mov.b r0,XH mov.b r0,YH.RTI16: S9xUnpackStatus RTI S9xFixCycles RTI CheckForIrqjmp RTI /* Removed in 1.39. See asmops.h */.emflag3: .word Emulation/* WAI */OpCB:#if 0 cmpb $0, IRQActive je .L5334#ifdef VAR_CYCLES addl $12, CYCLES#else addl $2, CYCLES#endif jmp MainAsmLoop.L5334:#endif mov #1,r0 add #-1,PC mov.b r0, WaitingForInterrupt mov.l Settings,r1 mov.b Shutdown,r0 tst r0,r0 bt .NoShutdown#ifdef ARMAPU mov #0,r2 mov.l NextEvent, CYCLES jmp @r13 mov.l r2,WaitAddress#else mov.l IAPU,r1 mov #0,r2 mov.b APUExecuting,r0 mov.l NextEvent, CYCLES tst r0,r0 mov.l r2,WaitAddress bt .EndWAIShutdown mov.l ICPU,r1 mov #0,r0 mov.b r0, CPUExecuting.WAITExecAPU:#ifdef DEBUGGER testb $2,APUFlags je .WAITNoAPUS9xTrace STORE_REGISTERS ccall S9xTraceAPU LOAD_REGISTERS.WAITNoAPUS9xTrace:#endif#ifdef SPC700_C mov.l IAPU,r1 SAVE_CYCLES mov.l APUPC,r0 PUSH_REGISTERS mov.b @r0,r0#else mov.b @APUPC,r0#endif mov.l .WAIAPUCycles,r1 extu.b r0,r0 mov.l .WAIApuOpcodes,r2 shll2 r0 mov.l @(r0,r1),r4 mov.l @(r0,r2),r0 mov.l APU,r1 mov.l APUCycles,r2 add r4,r2 jsr @r0 mov.l r2,APUCycles#ifdef SPC700_C POP_REGISTERS LOAD_CYCLES#endif mov.l APU,r1 mov.l NextEvent,r2 mov.l APUCycles,r3 cmp/ge r2,r3 bf .WAITExecAPU mov.l ICPU,r1 mov #1,r0 jmp @r13 mov.b r0, CPUExecuting.EndWAIShutdown: jmp @r13 nop .align 2.WAIAPUCycles: .long _S9xAPUCycles.WAIApuOpcodes: .long _S9xApuOpcodes#endif /* ARMAPU */.NoShutdown: jmp @r13#ifdef VAR_CYCLES add #12, CYCLES#else add #2, CYCLES#endif/* ??? */OpDB: mov.l Flags,r0 add #-1,PC or #DEBUG_MODE_FLAG, r0 jmp @r13 mov.l r0,FlagsOp42: jmp @r13 nop.globl _S9xOpcodesM1X1 .align 4_S9xOpcodesM1X1: .long Op00 .long Op01M1 .long Op02 .long Op03M1 .long Op04M1 .long Op05M1 .long Op06M1 .long Op07M1 .long Op08 .long Op09M1 .long Op0AM1 .long Op0B .long Op0CM1 .long Op0DM1 .long Op0EM1 .long Op0FM1 .long Op10 .long Op11M1 .long Op12M1 .long Op13M1 .long Op14M1 .long Op15M1 .long Op16M1 .long Op17M1 .long Op18 .long Op19M1 .long Op1AM1 .long Op1B .long Op1CM1 .long Op1DM1 .long Op1EM1 .long Op1FM1 .long Op20 .long Op21M1 .long Op22 .long Op23M1 .long Op24M1 .long Op25M1 .long Op26M1 .long Op27M1 .long Op28 .long Op29M1 .long Op2AM1 .long Op2B .long Op2CM1 .long Op2DM1 .long Op2EM1 .long Op2FM1 .long Op30 .long Op31M1 .long Op32M1 .long Op33M1 .long Op34M1 .long Op35M1 .long Op36M1 .long Op37M1 .long Op38 .long Op39M1 .long Op3AM1 .long Op3B .long Op3CM1 .long Op3DM1 .long Op3EM1 .long Op3FM1 .long Op40 .long Op41M1 .long Op42 .long Op43M1 .long Op44X1 .long Op45M1 .long Op46M1 .long Op47M1 .long Op48M1 .long Op49M1 .long Op4AM1 .long Op4B .long Op4C .long Op4DM1 .long Op4EM1 .long Op4FM1 .long Op50 .long Op51M1 .long Op52M1 .long Op53M1 .long Op54X1 .long Op55M1 .long Op56M1 .long Op57M1 .long Op58 .long Op59M1 .long Op5AX1 .long Op5B .long Op5C .long Op5DM1 .long Op5EM1 .long Op5FM1 .long Op60 .long Op61M1 .long Op62 .long Op63M1 .long Op64M1 .long Op65M1 .long Op66M1 .long Op67M1 .long Op68M1 .long Op69M1 .long Op6AM1 .long Op6B .long Op6C .long Op6DM1 .long Op6EM1 .long Op6FM1 .long Op70 .long Op71M1 .long Op72M1 .long Op73M1 .long Op74M1 .long Op75M1 .long Op76M1 .long Op77M1 .long Op78 .long Op79M1 .long Op7AX1 .long Op7B .long Op7C .long Op7DM1 .long Op7EM1 .long Op7FM1 .long Op80 .long Op81M1 .long Op82 .long Op83M1 .long Op84X1 .long Op85M1 .long Op86X1 .long Op87M1 .long Op88X1 .long Op89M1 .long Op8AM1 .long Op8B .long Op8CX1 .long Op8DM1 .long Op8EX1 .long Op8FM1 .long Op90 .long Op91M1 .long Op92M1 .long Op93M1 .long Op94X1 .long Op95M1 .long Op96X1 .long Op97M1 .long Op98M1 .long Op99M1 .long Op9A .long Op9BX1 .long Op9CM1 .long Op9DM1 .long Op9EM1 .long Op9FM1 .long OpA0X1 .long OpA1M1 .long OpA2X1 .long OpA3M1 .long OpA4X1 .long OpA5M1 .long OpA6X1 .long OpA7M1 .long OpA8X1 .long OpA9M1 .long OpAAX1 .long OpAB .long OpACX1 .long OpADM1 .long OpAEX1 .long OpAFM1 .long OpB0 .long OpB1M1 .long OpB2M1 .long OpB3M1 .long OpB4X1 .long OpB5M1 .long OpB6X1 .long OpB7M1 .long OpB8 .long OpB9M1 .long OpBAX1 .long OpBBX1 .long OpBCX1 .long OpBDM1 .long OpBEX1 .long OpBFM1 .long OpC0X1 .long OpC1M1 .long OpC2 .long OpC3M1 .long OpC4X1 .long OpC5M1 .long OpC6M1 .long OpC7M1 .long OpC8X1 .long OpC9M1 .long OpCAX1 .long OpCB .long OpCCX1 .long OpCDM1 .long OpCEM1 .long OpCFM1 .long OpD0 .long OpD1M1 .long OpD2M1 .long OpD3M1 .long OpD4 .long OpD5M1 .long OpD6M1
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