cpuops.s

SFC游戏模拟器 snes9x 1.43 的原代码

/* BCC */
Op90:
	Relative
	BranchCheck0 BCC
	GetNotCarry
	bf .BCC_EXIT
#ifdef VAR_CYCLES
	add #6,CYCLES
#else
	add #1,CYCLES
#endif
	mov.l PCBase,r3
	extu.w r4,PC
	add r3,PC
	CPUShutdown BCC
.BCC_EXIT:
	jmp @r13
	nop

/* BCS */
OpB0:
	Relative
	BranchCheck0 BCS
	GetNotCarry
	bt .BCS_EXIT
#ifdef VAR_CYCLES
	add #6,CYCLES
#else
	add #1,CYCLES
#endif
	mov.l PCBase,r3
	extu.w r4,PC
	add r3,PC
	CPUShutdown BCS
.BCS_EXIT:
	jmp @r13
	nop

/* BEQ */
OpF0:
	Relative
	BranchCheck2 BEQ
	extu.w r7,r3
	tst r3,r3
	bf .BEQ_EXIT
#ifdef VAR_CYCLES
	add #6,CYCLES
#else
	add #1,CYCLES
#endif
	mov.l PCBase,r3
	extu.w r4,PC
	add r3,PC
	CPUShutdown BEQ
.BEQ_EXIT:
	jmp @r13
	nop

/* BMI */
Op30:
	Relative
	BranchCheck1 BMI
	cmp/pz r7
	bt .BMI_EXIT
#ifdef VAR_CYCLES
	add #6,CYCLES
#else
	add #1,CYCLES
#endif
	mov.l PCBase,r3
	extu.w r4,PC
	add r3,PC
	CPUShutdown BMI
.BMI_EXIT:
	jmp @r13
	nop

/* BNE */
OpD0:
	Relative
	BranchCheck1 BNE
	extu.w r7,r3
	tst r3,r3
	bt .BNE_EXIT
#ifdef VAR_CYCLES
	add #6,CYCLES
#else
	add #1,CYCLES
#endif
	mov.l PCBase,r3
	extu.w r4,PC
	add r3,PC
	CPUShutdown BNE
.BNE_EXIT:
	jmp @r13
	nop

/* BPL */
Op10:
	Relative
	BranchCheck1 BPL
	cmp/pz r7
	bf .BPL_EXIT
#ifdef VAR_CYCLES
	add #6,CYCLES
#else
	add #1,CYCLES
#endif
	mov.l PCBase,r3
	extu.w r4,PC
	add r3,PC
	CPUShutdown BPL
.BPL_EXIT:
	jmp @r13
	nop

/* BRA */
Op80:
	Relative
#ifdef VAR_CYCLES
	add #6,CYCLES
#else
	add #1,CYCLES
#endif
	extu.w r4,PC
	mov.l PCBase,r3
	jmp @r13
	add r3,PC

/* BVC */
Op50:
	Relative
	BranchCheck0 BVC
	mov #Overflow,r1
	tst r1,FLAGS
	bf .BVC_EXIT:
#ifdef VAR_CYCLES
	add #6,CYCLES
#else
	add #1,CYCLES
#endif
	mov.l PCBase,r3
	extu.w r4,PC
	add r3,PC
	CPUShutdown BVC
.BVC_EXIT:
	jmp @r13
	nop

/* BVS */
Op70:
	Relative
	BranchCheck0 BVS
	mov #Overflow,r1
	tst r1,FLAGS
	bt .BVS_EXIT:
#ifdef VAR_CYCLES
	add #6,CYCLES
#else
	add #1,CYCLES
#endif
	mov.l PCBase,r3
	extu.w r4,PC
	add r3,PC
	CPUShutdown BVS
.BVS_EXIT:
	jmp @r13
	nop
	
/* BRL */
Op82:
	RelativeLong BRL
	extu.w r4,r4
	mov.l ICPU,r0
	mov.l @(16,r0),r2
	mov.l S9xSetPCBase,r3
	or r2,r4
	Xlink

/* CLC */
Op18:
	mov #~Carry,r0
#ifdef VAR_CYCLES
	add #6,CYCLES
#endif
	jmp @r13
	and r0,FLAGS

/* CLD */
OpD8:
	mov #~Decimal,r0
#ifdef VAR_CYCLES
	add #6,CYCLES
#endif
	jmp @r13
	and r0,FLAGS

/* CLI */
Op58:
	mov #~IRQ,r2
#ifdef VAR_CYCLES
	add #6,CYCLES
#endif
	mov.b IRQActive,r0
	tst r0,r0
	bt .CLI_EXIT
	/* XXX: test for Settings.DisableIRQ */
	mov.l S9xOpcode_IRQ,r3
	and r2,FLAGS
	Xlink
.CLI_EXIT:
	jmp @r13
	and r2,FLAGS

/* CLV */
OpB8:
	mov #~Overflow,r0
#ifdef VAR_CYCLES
	add #6,CYCLES
#endif
	jmp @r13
	and r0,FLAGS

/* DEX */
OpCAX1:
#ifdef VAR_CYCLES
	add #6,CYCLES
#endif
	mov.b XL,r0
#ifdef CPU_SHUTDOWN
	mov #0,r3
#endif
	add #-1,r0
#ifdef CPU_SHUTDOWN
	mov.l r3,WaitAddress
#endif
	mov.b r0,XL
	SetZNjmp r0

OpCAX0:
#ifdef VAR_CYCLES
	add #6,CYCLES
#endif
	mov.w XX,r0
#ifdef CPU_SHUTDOWN
	mov #0,r3
#endif
	add #-1,r0
#ifdef CPU_SHUTDOWN
	mov.l r3,WaitAddress
#endif
	mov.w r0,XX
	Set16ZNjmp r0

/* DEY */
Op88X1:
#ifdef VAR_CYCLES
	add #6,CYCLES
#endif
	mov.b YL,r0
#ifdef CPU_SHUTDOWN
	mov #0,r3
#endif
	add #-1,r0
#ifdef CPU_SHUTDOWN
	mov.l r3,WaitAddress
#endif
	mov.b r0,YL
	SetZNjmp r0

Op88X0:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	mov.w YY,r0
#ifdef CPU_SHUTDOWN
	mov #0,r3
#endif
	add #-1,r0
#ifdef CPU_SHUTDOWN
	mov.l r3,WaitAddress
#endif
	mov.w r0,YY
	Set16ZNjmp r0

/* INX */
OpE8X1:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	mov.b XL,r0
#ifdef CPU_SHUTDOWN
	mov #0,r3
#endif
	add #1,r0
#ifdef CPU_SHUTDOWN
	mov.l r3,WaitAddress
#endif
	mov.b r0, XL
	SetZNjmp r0

OpE8X0:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	mov.w XX,r0
#ifdef CPU_SHUTDOWN
	mov #0,r3
#endif
	add #1,r0
#ifdef CPU_SHUTDOWN
	mov.l r3,WaitAddress
#endif
	mov.w r0, XX
	Set16ZNjmp r0

/* INY */
OpC8X1:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	mov.b YL,r0
#ifdef CPU_SHUTDOWN
	mov #0,r3
#endif
	add #1,r0
#ifdef CPU_SHUTDOWN
	mov.l r3,WaitAddress
#endif
	mov.b r0, YL
	SetZNjmp r0

OpC8X0:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	mov.w YY,r0
#ifdef CPU_SHUTDOWN
	mov #0,r3
#endif
	add #1,r0
#ifdef CPU_SHUTDOWN
	mov.l r3,WaitAddress
#endif
	mov.w r0,YY
	Set16ZNjmp r0

/* NOP */
OpEA:
	jmp @r13
#ifdef VAR_CYCLES
	add #6,CYCLES
#else
	nop
#endif

/* PEA */
OpF4:
	Immediate16 PEA
	PushWordjmp PEA

/* PEI */
OpD4:
	DirectIndirect8 PEI
	extu.w r4,r0
	PushWordjmp PEI

/* PER */
Op62:
	RelativeLong PER
	extu.w r4,r0
	PushWordjmp PER

/* PHA */
Op48M1:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	extu.b A,r0
	PushBytejmp PHA

Op48M0:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	extu.w A,r0
	PushWordjmp PHA

/* PHB */
Op8B:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	mov.b DB, r0
	PushBytejmp PHB

/* PHD */
Op0B:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	mov.w DD, r0
	PushWordjmp PHD

/* PHK */
Op4B:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	mov.b PB, r0
	PushBytejmp PHK

/* PHP */
Op08:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	S9xPackStatus PHP
	extu.b FLAGS, r0
	PushBytejmp PHP

/* PHX */
OpDAX1:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	mov.b XL, r0
	PushBytejmp PHX

OpDAX0:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	mov.w XX, r0
	PushWordjmp PHX

/* PHY */
Op5AX1:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	mov.b YL, r0
	PushBytejmp PHY

Op5AX0:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	mov.w YY, r0
	PushWordjmp PHY

/* PLA */
Op68M1:
#ifdef VAR_CYCLES
	add #12, CYCLES
#endif
	PullByte PLA
	extu.b A,r1
	add r0,A
	sub r1,A
	SetZNjmp A

Op68M0:
#ifdef VAR_CYCLES
	add #12, CYCLES
#endif
	PullWord PLA
	extu.w r0,A
	Set16ZNjmp A

/* PLB */
OpAB:
#ifdef VAR_CYCLES
	add #12, CYCLES
#endif
	PullByte PLB
	mov.b r0, DB
	extu.b r0,r1
	mov.l ICPU,r2
	shll16 r1
	mov.l r1,@(20,r2)
	SetZNjmp r0

/* PLD */
Op2B:
#ifdef VAR_CYCLES
	add #12, CYCLES
#endif
	PullWord PLD
	mov.w r0 DD
	Set16ZNjmp r0
	
/* PLP */
Op28:
#ifdef VAR_CYCLES
	add #12, CYCLES
#endif
	PullByte PLP
	extu.b FLAGS,r1
	add r0,FLAGS
	mov #IndexFlag,r2
	sub r1,FLAGS
	tst r2,r0
	bt .PLP16
	mov #0,r0
	mov.b r0,XH
	mov.b r0,YH
.PLP16:
	S9xUnpackStatus PLP
	S9xFixCycles PLP
	CheckForIrqjmp PLP /* Removed in 1.39. See asmops.h */

/* PLX */
OpFAX1:
#ifdef VAR_CYCLES
	add #12, CYCLES
#endif
	PullByte PLX
	mov.b r0, XL
	SetZNjmp r0

OpFAX0:
#ifdef VAR_CYCLES
	add #12, CYCLES
#endif
	PullWord PLX
	mov.w r0, XX
	Set16ZNjmp r0

/* PLY */
Op7AX1:
#ifdef VAR_CYCLES
	add #12, CYCLES
#endif
	PullByte PLY
	mov.b r0, YL
	SetZNjmp r0

Op7AX0:
#ifdef VAR_CYCLES
	add #12, CYCLES
#endif
	PullWord PLY
	mov.w r0, YY
	Set16ZNjmp r0

/* SEC */
Op38:
	mov #Carry,r0
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	jmp @r13
	or r0,FLAGS

/* SED */
OpF8:
	
	mov #Decimal,r0
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	jmp @r13
	or r0,FLAGS

/* SEI */
Op78:
	mov #IRQ,r0
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	jmp @r13
	or r0,FLAGS

/* TAX */
OpAAX1:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	extu.b A,r0
	mov.b r0, XL
	SetZNjmp r0

OpAAX0:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	extu.w A,r0
	mov.w r0, XX
	Set16ZNjmp r0

/* TAY */
OpA8X1:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	extu.b A,r0
	mov.b r0, YL
	SetZNjmp r0

OpA8X0:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	extu.w A,r0
	mov.w r0, YY
	Set16ZNjmp r0

/* TCD */
Op5B:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	extu.w A,r0
	mov.w r0, DD
	Set16ZNjmp r0

/* TCS */
Op1B:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	extu.w A,r0
	mov #Emulation/4,r1
	mov.w r0, SS
	shll2 r1
	tst r1,FLAGS16
	bt .TCS_EXIT
	mov #1,r0
	mov.b r0,SH
.TCS_EXIT:
	jmp @r13
	nop

/* TDC */
Op7B:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	mov.w DD, r0
	extu.w r0,A
	Set16ZNjmp A

/* TSC */
Op3B:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	mov.w SS, r0
	extu.w r0,A
	Set16ZNjmp A

/* TSX */
OpBAX1:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	mov.b SL, r0
	mov.b r0, XL
	SetZNjmp r0

OpBAX0:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	mov.w SS, r0
	mov.w r0, XX
	Set16ZNjmp r0

/* TXA */
Op8AM1:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	mov.b XL, r0
	extu.b A,r1
	extu.b r0,r0
	sub r1,A
	add r0,A
	SetZNjmp A

Op8AM0:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	mov.w XX, r0
	extu.w r0,A
	Set16ZNjmp A

/* TXS */
Op9A:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	mov.w XX, r0
	mov #Emulation/4,r1
	mov.w r0, SS
	shll2 r1
	tst r1,FLAGS16
	bt .TXS_EXIT
	mov #1,r0
	mov.b r0,SH
.TXS_EXIT:
	jmp @r13
	nop

/* TXY */
Op9BX1:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	mov.b XL, r0
	mov.b r0, YL
	SetZNjmp r0

Op9BX0:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	mov.w XX, r0
	mov.w r0, YY
	Set16ZNjmp r0

/* TYA */
Op98M1:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	mov.b YL, r0
	extu.b A,r1
	extu.b r0,r0
	sub r1,A
	add r0,A
	SetZNjmp A

Op98M0:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	mov.w YY, r0
	extu.w r0,A
	Set16ZNjmp A

/* TYX */
OpBBX1:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	mov.b YL, r0
	mov.b r0, XL
	SetZNjmp r0

OpBBX0:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	mov.w YY, r0
	mov.w r0, XX
	Set16ZNjmp r0

/* XCE */
OpFB:
#ifdef VAR_CYCLES
	add #6, CYCLES
#endif
	mov FLAGS16, r0
	mov.w .notemcymask,r1
	and r1,FLAGS16
	tst #Carry,r0
	mov.w .emflag0,r1
	bt .XCE_NO_CARRY
	or r1,FLAGS16
.XCE_NO_CARRY:
	tst r1,r0
	bt/s .XCE_NO_EMU
	tst r1,FLAGS
	add #Carry,FLAGS
.XCE_NO_EMU:
	bt/s .XCE_NO_EMULATION2
	mov #IndexFlag,r1
	mov #MemoryFlag|IndexFlag,r0
	or r0,FLAGS
	mov #1,r0
	mov.b r0,SH
.XCE_NO_EMULATION2:
	tst r1,FLAGS
	bt .XCE_NO_INDEX
	mov #0,r0
	mov.b r0, XH
	mov.b r0, YH
.XCE_NO_INDEX:
	S9xFixCycles XCE
	jmp @r13
	nop

.emflag0:
	.word	Emulation

Op00:
#ifdef DEBUGGER
	testb $TRACE_FLAG, Flags
	je .BRK_NO_TRACE
	pushl $.LC0
	ccall S9xTraceMessage
	addl $4,%esp
.BRK_NO_TRACE:
#endif
	mov #1,r0
	mov.b r0,BRKTriggered
	mov.w .emflag,r0
	tst r0,FLAGS16
	bf .BRK_EMULATION
	mov.b PB, r0
	PushByte BRK1
	mov.l PCBase,r0
	neg r0,r0
	add PC, r0
	add #1,r0
	PushWord BRK2
	
	S9xPackStatus BRK
	extu.b FLAGS, r0
	mov #Decimal|IRQ,r1
	or r1,FLAGS
	add #-Decimal, FLAGS
	
	PushByte BRK3
	mov.l ICPU,r3
	mov #0,r0
	mov.l r0,@(16,r3)
	mov.b r0,PB
#ifdef VAR_CYCLES
	add #12, CYCLES
#else
	add #8, CYCLES
#endif
	mov.l S9xGetWord,r3
	mov #-0x1a,r4
	jsr @r3
	extu.w r4,r4
	mov.l S9xSetPCBase,r3
	extu.w r0,r4
	Xlink
.BRK_EMULATION:
	mov.l PCBase,r0
	neg r0,r0
	add PC, r0
	add #1,r0
	PushWord BRK2
	
	S9xPackStatus BRK2
	extu.b FLAGS, r0
	mov #Decimal|IRQ,r1
	or r1,FLAGS
	add #-Decimal, FLAGS
	
	PushByte BRK3
	mov.l ICPU,r3
	mov #0,r0
	mov.l r0,@(16,r3)
	mov.b r0,PB
#ifdef VAR_CYCLES
	add #6, CYCLES
#else
	add #6, CYCLES
#endif
	mov.l S9xGetWord,r3
	mov #-2,r4
	jsr @r3
	extu.w r4,r4
	mov.l S9xSetPCBase,r3
	extu.w r0,r4
	Xlink

.notemcymask:
	.word	~(Emulation|Carry)
.emflag:
	.word	Emulation

#ifdef DEBUGGER
	.align 4
.LC0:
	.ascii	"*** BRK"
	.byte 0
#endif

	
.globl S9xOpcode_IRQ_r
S9xOpcode_IRQ_r:
#ifdef DEBUGGER
	testb $TRACE_FLAG, Flags
	je .IRQ_NO_TRACE
	pushl $.LC1
	ccall S9xTraceMessage
	addl $4, %esp
.IRQ_NO_TRACE:
#endif
	mov.w .emflag1,r0
	sts.l pr,@-r15
	tst r0,FLAGS16
	bf .IRQ_EMULATION
	mov.b PB, r0
	PushByte IRQ1
	mov.l PCBase,r0
	neg r0,r0
	add PC, r0
	PushWord IRQ2
	
	S9xPackStatus IRQ
	extu.b FLAGS, r0
	mov #Decimal|IRQ,r1
	or r1,FLAGS
	add #-Decimal, FLAGS
	
	PushByte IRQ3
	mov.l ICPU,r3
	mov #0,r0
	mov.l r0,@(16,r3)
	mov.b r0,PB
#ifdef VAR_CYCLES
	add #12, CYCLES
#else
	add #8, CYCLES
#endif
	mov.l Settings,r3
	add #82,r3	! Settings.SA1
	mov.b @r3,r0
	tst r0,r0
	bt .noirqsa1vector
	mov.l .FillRAM2,r3
	mov.l @r3,r3
	mov.w .n2209,r0
	add r0,r3
	mov.b @r3,r0
	tst #0x40,r0
	bt .noirqsa1vector
	add #5,r3
	lds.l @r15+,pr
	mov.w @r3,r4
	mov.l S9xSetPCBase,r3
	jmp @r3
	extu.w r4,r4
.noirqsa1vector:
	mov.l S9xGetWord,r3
	mov #-0x12,r4
	jsr @r3
	extu.w r4,r4
	mov.l S9xSetPCBase,r3
	lds.l @r15+,pr
	jmp @r3
	extu.w r0,r4
.IRQ_EMULATION:
	mov.l PCBase,r0
	neg r0,r0
	add PC, r0
	PushWord IRQ4
	
	S9xPackStatus IRQ2
	extu.b FLAGS, r0
	mov #Decimal|IRQ,r1
	or r1,FLAGS
	add #-Decimal, FLAGS
	
	PushByte IRQ5
	mov.l ICPU,r3
	mov #0,r0
	mov.l r0,@(16,r3)
	mov.b r0,PB
#ifdef VAR_CYCLES
	add #6, CYCLES
#else
	add #6, CYCLES
#endif
	mov.l S9xGetWord,r3
	mov #-0x2,r4
	jsr @r3
	extu.w r4,r4
	mov.l S9xSetPCBase,r3
	lds.l @r15+,pr
	jmp @r3
	extu.w r0,r4

.emflag1:
	.word	Emulation