sdram.c

ARM9内核的philip公司的LPC3180初始化SDRAM的驱动代码

#include "sdram.h"

void sdram_init(unsigned char sdram_size)
{
  volatile unsigned int i;
  volatile unsigned int temp;
  
  SDRAMCLK_CTRL_REG.HCLKDELAY_DELAY = 0x7;
  MPMCCONTROL_REG.SDRAM_ENABLE = 1;
  MPMCCONFIG_REG.ENDIAN = 0;
  MPMCAHB_CONTROL_0_REG.E = 1;
  MPMCAHB_CONTROL_2_REG.E = 1;
  MPMCAHB_CONTROL_3_REG.E = 1;
  MPMCAHB_CONTROL_4_REG.E = 1;
  switch (sdram_size)
  {
  case SDRAM_SIZE_16MB:
    MPMCDYNAMIC_CONFIG_0_REG.AM = SDRAM_ADDRESS_MAP_16MB; break;
  case SDRAM_SIZE_64MB:
    MPMCDYNAMIC_CONFIG_0_REG.AM = SDRAM_ADDRESS_MAP_64MB; break;
  case SDRAM_SIZE_128MB:
    MPMCDYNAMIC_CONFIG_0_REG.AM = SDRAM_ADDRESS_MAP_128MB; break;
  default:
    MPMCDYNAMIC_CONFIG_0_REG.AM = SDRAM_ADDRESS_MAP_32MB; 
  }
  MPMCDYNAMIC_CONFIG_0_REG.MD = 2; // low power SDR SDRAM
#if (SDRAM_MODE_REG_CAS_VALUE == SDRAM_MODE_REG_CAS2)
  MPMCDYNAMIC_RAS_CAS_0_REG.CAS = SDRAM_CAS2;
#else
  MPMCDYNAMIC_RAS_CAS_0_REG.CAS = SDRAM_CAS3;
#endif
  MPMCDYNAMIC_RAS_CAS_0_REG.RAS = SDRAM_tRCD_min;
  MPMCDYNAMIC_TRP_REG.tRP = SDRAM_tRP_min-1;
  MPMCDYNAMIC_TRAS_REG.tRAS = SDRAM_tRAS_min-1;
  MPMCDYNAMIC_TSREX_REG.tSREX = SDRAM_tSREX_min-1;
  MPMCDYNAMIC_TWR_REG.tWR = SDRAM_tWR_min-1;
  MPMCDYNAMIC_TRC_REG.tRC = SDRAM_tRC_min-1;
  MPMCDYNAMIC_TRFC_REG.tRFC = SDRAM_tRFC_min-1;
  MPMCDYNAMIC_TXSR_REG.tXSR = SDRAM_tXSR_min-1;
  MPMCDYNAMIC_TRRD_REG.tRRD = SDRAM_tRRD_min-1;
  MPMCDYNAMIC_TMRD_REG.tMRD = SDRAM_tMRD_min-1;
  MPMCDYNAMIC_TCDLR_REG.tCDLR = SDRAM_tCDLR_min-1;
  for (i = 0; i < 100; i++);
  MPMCDYNAMIC_CONTROL = SDRAM_CMD_NOP;
  for (i = 0; i < 200; i++);
  MPMCDYNAMIC_CONTROL = SDRAM_CMD_PALL;
  MPMCDYNAMIC_REFRESH_REG.REFRESH = 2;
  for (i = 0; i < 15; i++);
  MPMCDYNAMIC_REFRESH_REG.REFRESH = 101; // 64ms for 4096 rows -> 15.625us/row -> 1625 clock cycles -> 101 16-cycle time periods
  MPMCDYNAMIC_CONTROL = SDRAM_CMD_MODE;
  switch (sdram_size)
  {
  case SDRAM_SIZE_16MB:
    temp = *((unsigned int*)SDRAM_MODE_REG_VALUE_16MB); break; // address lines issue register op-code 
  case SDRAM_SIZE_64MB:
    temp = *((unsigned int*)SDRAM_MODE_REG_VALUE_64MB); break; // address lines issue register op-code 
  case SDRAM_SIZE_128MB:
    temp = *((unsigned int*)SDRAM_MODE_REG_VALUE_128MB); break; // address lines issue register op-code 
  default:
    temp = *((unsigned int*)SDRAM_MODE_REG_VALUE_32MB); break; // address lines issue register op-code 
  }
  MPMCDYNAMIC_CONTROL = SDRAM_CMD_MODE;
  switch (sdram_size)
  {
  case SDRAM_SIZE_16MB:
    temp = *((unsigned int*)SDRAM_EMODE_REG_VALUE_16MB); break; // address lines issue register op-code 
  case SDRAM_SIZE_64MB:
    temp = *((unsigned int*)SDRAM_EMODE_REG_VALUE_64MB); break; // address lines issue register op-code 
  case SDRAM_SIZE_128MB:
    temp = *((unsigned int*)SDRAM_EMODE_REG_VALUE_128MB); break; // address lines issue register op-code 
  default:
    temp = *((unsigned int*)SDRAM_EMODE_REG_VALUE_32MB); break; // address lines issue register op-code 
  }
  MPMCDYNAMIC_CONTROL = SDRAM_CMD_NORMAL;
  MPMCAHB_TIME_0_REG.AHBTIMEOUT = 100;
  MPMCAHB_TIME_2_REG.AHBTIMEOUT = 400;
  MPMCAHB_TIME_3_REG.AHBTIMEOUT = 400;
  MPMCAHB_TIME_4_REG.AHBTIMEOUT = 400;  
}