sdram.h

ARM9内核的philip公司的LPC3180初始化SDRAM的驱动代码

/*******************************************************************************
 * Copyright (c) 2006, PHYTEC America LLC
 * 
 * contact : [e-mail]; http://www.phytec.com
 *
 * THIS SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * PHYTEC BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY DUE TO THE USE 
 * OF THIS SOFTWARE. YOU MAY FREELY MODIFY AND DISTRIBUTE THIS SOFTWARE
 * PROVIDED THE ORIGINAL COPYRIGHT NOTICE IS MAINTAINED.
 * 
 * ABOUT : phyCORE-LPC3180 SDR SDRAM initialization routines.
 ******************************************************************************/

#ifndef __SDRAM
#define __SDRAM

typedef unsigned long u32;

typedef struct
{
  u32 SDRAM_HCLK            : 1;
  u32 DDR_SEL               : 1;
  u32 DDR_DQSIN_DELAY       : 5;
  u32 RTC_TICK_EN           : 1;
  u32 SW_DDR_CAL            : 1;
  u32 DDR_SDRAM_SENSITIVITY : 3;
  u32 DELAY_ADDER_STATUS    : 1;
  u32 HCLKDELAY_DELAY       : 5;
  u32 SW_DDR_RESET          : 1;
  u32 SDRAM_PIN_SPEED1      : 1;
  u32 SDRAM_PIN_SPEED2      : 1;
  u32 SDRAM_PIN_SPEED3      : 1;
  u32                       : 10;
} __SDRAMCLK_CTRL_REG;

typedef struct
{
  u32 SDRAM_ENABLE    : 1;
  u32                 : 1;
  u32 LOW_POWER_MODE  : 1;
  u32                 : 29;
} __MPMCCONTROL_REG;

typedef struct
{
  u32 BUSY  : 1;
  u32       : 1;
  u32 SA    : 1;
  u32       : 29;
} __MPMCSTATUS_REG;

typedef struct
{
  u32 ENDIAN : 1;
  u32        : 31;
} __MPMCCONFIG_REG;

typedef struct
{
  u32 CE    : 1;
  u32 CS    : 1;
  u32 SR    : 1;
  u32 SRMMC : 1;
  u32 IMMC  : 1;
  u32 MMC   : 1;
  u32       : 1;
  u32 I     : 2;
  u32       : 4;
  u32 DP    : 1;
  u32       : 18;
} __MPMCDYNAMIC_CONTROL_REG;

typedef struct
{
  u32 REFRESH : 11;
  u32         : 21;
} __MPMCDYNAMIC_REFRESH_REG;

typedef struct
{
  u32 SRD : 2;
  u32     : 2;
  u32 SRP : 1;
  u32     : 3;
  u32 DRD : 2;
  u32     : 2;
  u32 DRP : 1;
  u32     : 19;
} __MPMCDYNAMIC_READ_CONFIG_REG;

typedef struct
{
  u32 tRP : 4;
  u32     : 28;
} __MPMCDYNAMIC_TRP_REG;

typedef struct
{
  u32 tRAS : 4;
  u32       : 28;
} __MPMCDYNAMIC_TRAS_REG;

typedef struct
{
  u32 tSREX : 7;
  u32       : 25;
} __MPMCDYNAMIC_TSREX_REG;

typedef struct
{
  u32 tWR : 4;
  u32     : 28;
} __MPMCDYNAMIC_TWR_REG;

typedef struct
{
  u32 tRC : 5;
  u32     : 27;
} __MPMCDYNAMIC_TRC_REG;

typedef struct
{
  u32 tRFC : 5;
  u32     : 27;
} __MPMCDYNAMIC_TRFC_REG;

typedef struct
{
  u32 tXSR : 8;
  u32      : 24;
} __MPMCDYNAMIC_TXSR_REG;

typedef struct
{
  u32 tRRD : 4;
  u32      : 28;
} __MPMCDYNAMIC_TRRD_REG;

typedef struct
{
  u32 tMRD : 4;
  u32      : 28;
} __MPMCDYNAMIC_TMRD_REG;

typedef struct
{
  u32 tCDLR : 4;
  u32       : 28;
} __MPMCDYNAMIC_TCDLR_REG;

typedef struct
{
  u32 MD  : 3;
  u32     : 4;
  u32 AM  : 8;
  u32     : 5;
  u32 P   : 1;
  u32     : 11;
} __MPMCDYNAMIC_CONFIG_0_REG;

typedef struct
{
  u32 RAS : 4;
  u32     : 3;
  u32 CAS : 4;
  u32     : 21;
} __MPMCDYNAMIC_RAS_CAS_0_REG;

typedef struct
{
  u32 E : 1;
  u32   : 31;
} __MPMCAHB_CONTROL_0_REG;

typedef struct
{
  u32 E : 1;
  u32   : 31;
} __MPMCAHB_CONTROL_2_REG;

typedef struct
{
  u32 E : 1;
  u32   : 31;
} __MPMCAHB_CONTROL_3_REG;

typedef struct
{
  u32 E : 1;
  u32   : 31;
} __MPMCAHB_CONTROL_4_REG;

typedef struct
{
  u32   : 1;
  u32 S : 1;
  u32   : 30;
} __MPMCAHB_STATUS_0_REG;

typedef struct
{
  u32   : 1;
  u32 S : 1;
  u32   : 30;
} __MPMCAHB_STATUS_2_REG;

typedef struct
{
  u32   : 1;
  u32 S : 1;
  u32   : 30;
} __MPMCAHB_STATUS_3_REG;

typedef struct
{
  u32   : 1;
  u32 S : 1;
  u32   : 30;
} __MPMCAHB_STATUS_4_REG;

typedef struct
{
  u32 AHBTIMEOUT : 10;
  u32            : 22;
} __MPMCAHB_TIME_0_REG;

typedef struct
{
  u32 AHBTIMEOUT : 10;
  u32            : 22;
} __MPMCAHB_TIME_2_REG;

typedef struct
{
  u32 AHBTIMEOUT : 10;
  u32            : 22;
} __MPMCAHB_TIME_3_REG;

typedef struct
{
  u32 AHBTIMEOUT : 10;
  u32            : 22;
} __MPMCAHB_TIME_4_REG;

#define SDRAMCLK_CTRL_REG               (*(volatile __SDRAMCLK_CTRL_REG*)           (0x40004068))
#define MPMCCONTROL_REG                 (*(volatile __MPMCCONTROL_REG*)             (0x31080000))
#define MPMCSTATUS_REG                  (*(volatile __MPMCSTATUS_REG*)              (0x31080004))
#define MPMCCONFIG_REG                  (*(volatile __MPMCCONFIG_REG*)              (0x31080008))
#define MPMCDYNAMIC_CONTROL_REG         (*(volatile __MPMCDYNAMIC_CONTROL_REG*)     (0x31080020))
#define MPMCDYNAMIC_CONTROL             (*(volatile unsigned long*)                 (0x31080020))
#define MPMCDYNAMIC_REFRESH_REG         (*(volatile __MPMCDYNAMIC_REFRESH_REG*)     (0x31080024))
#define MPMCDYNAMIC_READ_CONFIG_REG     (*(volatile __MPMCDYNAMIC_READ_CONFIG_REG*) (0x31080028))
#define MPMCDYNAMIC_TRP_REG             (*(volatile __MPMCDYNAMIC_TRP_REG*)         (0x31080030))
#define MPMCDYNAMIC_TRAS_REG            (*(volatile __MPMCDYNAMIC_TRAS_REG*)        (0x31080034))
#define MPMCDYNAMIC_TSREX_REG           (*(volatile __MPMCDYNAMIC_TSREX_REG*)       (0x31080038))
#define MPMCDYNAMIC_TWR_REG             (*(volatile __MPMCDYNAMIC_TWR_REG*)         (0x31080044))
#define MPMCDYNAMIC_TRC_REG             (*(volatile __MPMCDYNAMIC_TRC_REG*)         (0x31080048))
#define MPMCDYNAMIC_TRFC_REG            (*(volatile __MPMCDYNAMIC_TRFC_REG*)        (0x3108004C))
#define MPMCDYNAMIC_TXSR_REG            (*(volatile __MPMCDYNAMIC_TXSR_REG*)        (0x31080050))
#define MPMCDYNAMIC_TRRD_REG            (*(volatile __MPMCDYNAMIC_TRRD_REG*)        (0x31080054))
#define MPMCDYNAMIC_TMRD_REG            (*(volatile __MPMCDYNAMIC_TMRD_REG*)        (0x31080058))
#define MPMCDYNAMIC_TCDLR_REG           (*(volatile __MPMCDYNAMIC_TCDLR_REG*)       (0x3108005C))
#define MPMCDYNAMIC_CONFIG_0_REG        (*(volatile __MPMCDYNAMIC_CONFIG_0_REG*)    (0x31080100))
#define MPMCDYNAMIC_RAS_CAS_0_REG       (*(volatile __MPMCDYNAMIC_RAS_CAS_0_REG*)   (0x31080104))
#define MPMCAHB_CONTROL_0_REG           (*(volatile __MPMCAHB_CONTROL_0_REG*)       (0x31080400))
#define MPMCAHB_CONTROL_2_REG           (*(volatile __MPMCAHB_CONTROL_2_REG*)       (0x31080440))
#define MPMCAHB_CONTROL_3_REG           (*(volatile __MPMCAHB_CONTROL_3_REG*)       (0x31080460))
#define MPMCAHB_CONTROL_4_REG           (*(volatile __MPMCAHB_CONTROL_4_REG*)       (0x31080480))
#define MPMCAHB_STATUS_0_REG            (*(volatile __MPMCAHB_STATUS_0_REG*)        (0x31080404))
#define MPMCAHB_STATUS_2_REG            (*(volatile __MPMCAHB_STATUS_2_REG*)        (0x31080444))
#define MPMCAHB_STATUS_3_REG            (*(volatile __MPMCAHB_STATUS_3_REG*)        (0x31080464))
#define MPMCAHB_STATUS_4_REG            (*(volatile __MPMCAHB_STATUS_4_REG*)        (0x31080484))
#define MPMCAHB_TIME_0_REG              (*(volatile __MPMCAHB_TIME_0_REG*)          (0x31080408))
#define MPMCAHB_TIME_2_REG              (*(volatile __MPMCAHB_TIME_2_REG*)          (0x31080448))
#define MPMCAHB_TIME_3_REG              (*(volatile __MPMCAHB_TIME_3_REG*)          (0x31080468))
#define MPMCAHB_TIME_4_REG              (*(volatile __MPMCAHB_TIME_4_REG*)          (0x31080488))



/******************************************************************************* 
 * SDRAM Timing Parameters
 * Note : these are based on Micron mobile 1.8V SDRAM, 125MHz operating 
 * frequency! These values also assume the SDRAM bus is operating at 104MHz.
 ******************************************************************************/

#define SDRAM_tRFcyc      64e-3
#define SDRAM_ROW_CNT     4096

#define SDRAM_tRP_min     2     // 19e-9 -> 2 cycles @ 104MHz
#define SDRAM_tRAS_min    5     // 48e-9 -> 5 cycles @ 104MHz
#define SDRAM_tSREX_min   9     // 80e-9 -> 9 cycles @ 104MHz
#define SDRAM_tWR_min     2     // 15e-9 -> 2 cycles @ 104MHz
#define SDRAM_tRC_min     9     // 80e-9 -> 9 cycles @ 104MHz
#define SDRAM_tRFC_min    9     // 80e-9 -> 9 cycles @ 104MHz
#define SDRAM_tXSR_min    9     // 80e-9 -> 9 cycles @ 104MHz
#define SDRAM_tRRD_min    2     // 16e-9 -> 2 cycles @ 104MHz
#define SDRAM_tMRD_min    2     // 2 cycles @ 104MHz
#define SDRAM_tCDLR_min   1     // 1 cycle @ 104MHz
#define SDRAM_tRCD_min    2     // 19e-9 -> 2 cycles @ 104MHz

#define SDRAM_CAS2        4
#define SDRAM_CAS3        6

#define SDRAM_CMD_MODE    ((0x1 << 7) + (0x1 << 4) + (0x1 << 1) + 0x1)
#define SDRAM_CMD_NOP     ((0x3 << 7) + (0x1 << 4) + (0x1 << 1) + 0x1)
#define SDRAM_CMD_PALL    ((0x2 << 7) + (0x1 << 4) + (0x1 << 1) + 0x1)
#define SDRAM_CMD_NORMAL  (0x1 << 4)

/* BEGIN : Address to pin mapping definitions */
#define SDRAM_MAP_ROW_16MB(x)           (x << 10)
#define SDRAM_MAP_ROW_32MB(x)           (x << 11)
#define SDRAM_MAP_ROW_64MB(x)           (x << 11)
#define SDRAM_MAP_ROW_128MB(x)          (x << 12)

#define SDRAM_MAP_BANK_16MB(BA1,BA0)    ((BA1 << 23) | (BA0 << 22))
#define SDRAM_MAP_BANK_32MB(BA1,BA0)    ((BA1 << 23) | (BA0 << 24))
#define SDRAM_MAP_BANK_64MB(BA1,BA0)    ((BA1 << 25) | (BA0 << 24))
#define SDRAM_MAP_BANK_128MB(BA1,BA0)   ((BA1 << 25) | (BA0 << 26))

#define SDRAM_SELECT                    (1 << 31)
/* END   : Address to pin mapping definitions */

/* Modify SDRAM_MODE_REG_CAS_VALUE to either SDRAM_MODE_REG_CAS2 or 
 * SDRAM_MODE_REG_CAS3 to change the SDRAM CAS latency. Note that the 125MHz
 * SDRAM on the phyCORE-LPC3180 can handle CAS2, however, 104MHz SDRAM must
 * use CAS3. 
 */
#define SDRAM_MODE_REG_CAS_VALUE        SDRAM_MODE_REG_CAS2

/* DO NOT MODIFY */
#define SDRAM_MODE_REG_CAS(x)           (x << 4)
#define SDRAM_MODE_REG_CAS2             0x2
#define SDRAM_MODE_REG_CAS3             0x3


#define SDRAM_EMODE_REG_DS(x)           (x << 5)
#define SDRAM_EMODE_REG_DS_FULL         0x0
#define SDRAM_EMODE_REG_DS_HALF         0x1
#define SDRAM_EMODE_REG_DS_QUARTER      0x2
#define SDRAM_EMODE_REG_DS_EIGHTH       0x3

#define SDRAM_MODE_REG_VALUE_16MB      (SDRAM_SELECT | SDRAM_MAP_BANK_16MB(0,0) | SDRAM_MAP_ROW_16MB(SDRAM_MODE_REG_CAS(SDRAM_MODE_REG_CAS_VALUE)))
#define SDRAM_EMODE_REG_VALUE_16MB     (SDRAM_SELECT | SDRAM_MAP_BANK_16MB(1,0) | SDRAM_MAP_ROW_16MB(SDRAM_EMODE_REG_DS(SDRAM_EMODE_REG_DS_FULL)))
#define SDRAM_MODE_REG_VALUE_32MB      (SDRAM_SELECT | SDRAM_MAP_BANK_32MB(0,0) | SDRAM_MAP_ROW_32MB(SDRAM_MODE_REG_CAS(SDRAM_MODE_REG_CAS_VALUE)))
#define SDRAM_EMODE_REG_VALUE_32MB     (SDRAM_SELECT | SDRAM_MAP_BANK_32MB(1,0) | SDRAM_MAP_ROW_32MB(SDRAM_EMODE_REG_DS(SDRAM_EMODE_REG_DS_FULL)))
#define SDRAM_MODE_REG_VALUE_64MB      (SDRAM_SELECT | SDRAM_MAP_BANK_64MB(0,0) | SDRAM_MAP_ROW_64MB(SDRAM_MODE_REG_CAS(SDRAM_MODE_REG_CAS_VALUE)))
#define SDRAM_EMODE_REG_VALUE_64MB     (SDRAM_SELECT | SDRAM_MAP_BANK_64MB(1,0) | SDRAM_MAP_ROW_64MB(SDRAM_EMODE_REG_DS(SDRAM_EMODE_REG_DS_FULL)))
#define SDRAM_MODE_REG_VALUE_128MB     (SDRAM_SELECT | SDRAM_MAP_BANK_128MB(0,0) | SDRAM_MAP_ROW_128MB(SDRAM_MODE_REG_CAS(SDRAM_MODE_REG_CAS_VALUE)))
#define SDRAM_EMODE_REG_VALUE_128MB    (SDRAM_SELECT | SDRAM_MAP_BANK_128MB(1,0) | SDRAM_MAP_ROW_128MB(SDRAM_EMODE_REG_DS(SDRAM_EMODE_REG_DS_FULL)))

#define SDRAM_ADDRESS_MAP_16MB    0xA5
#define SDRAM_ADDRESS_MAP_32MB    0xA9
#define SDRAM_ADDRESS_MAP_64MB    0xAD
#define SDRAM_ADDRESS_MAP_128MB   0xB1

#define SDRAM_SIZE_16MB           0
#define SDRAM_SIZE_32MB           1
#define SDRAM_SIZE_64MB           2
#define SDRAM_SIZE_128MB          3

/* Initialized the SDR SDRAM controller & SDRAM itself. Select sdram_size to be:
 * SDRAM_SIZE_16MB
 * SDRAM_SIZE_32MB
 * SDRAM_SIZE_64MB
 * SDRAM_SIZE_128MB
 */
void sdram_init(unsigned char sdram_size);

#endif