386arch.gml

开放源码的编译器open watcom 1.6.0版的源代码

.chap 386 Architecture
.*
.section Registers
.*
.np
.ix 'registers'
The register model for the 386 microprocessor consists of 8 32-bit
general-purpose registers used primarily to contain operands for
arithmetic and logical operations,
6 segment registers which determine which segments of memory are
addressable,
and status and instruction registers used to record and alter aspects
of the 386 processor state.
.*
.section General Registers
.*
.np
.ix 'general registers'
The general-purpose registers are named EAX, EBX, ECX, EDX, EBP, ESP,
ESI and EDI.
The low-order word of these registers have different names and can be
used for handling 16-bit data items.
The word registers are called AX, BX, CX, DX, BP, SP, SI and DI.
Each byte of the word registers AX, BX, CX and DX has a separate name.
The byte registers are named AH, AL, BH, BL, CH, CL, DH and DL and are
useful for handling characters and other 8-bit data.
:image depth='7.0i' file='386ARCH1' text='386 Registers'.
.np
All general-purpose registers can be used for addressing calculations
and for results of most arithmetic and logical calculations.
However, each register has specific functions as well.
Instructions that use specific registers include double-precision
multiply and divide, i/o, string instructions, translate, loop,
variable shift and rotate, and stack operations.
.*
.beglevel
.*
.section The EAX Register
.*
.np
.ix 'registers' 'EAX'
.ix 'EAX register'
The EAX register is known as the accumulator.
Some arithmetic operations implicitly use this register.
For example, the multiply and divide instructions require the use of
the EAX register.
The input/output instructions also use this register for transferring
data from input/output devices to the 386 processor.
.*
.section The EBX Register
.*
.np
.ix 'registers' 'EBX'
.ix 'EBX register'
The EBX register (along with the DS segment register) is used to point
to the translate table for the XLAT instruction.
.*
.section The ECX Register
.*
.np
.ix 'registers' 'ECX'
.ix 'ECX register'
The ECX register is known as the count register.
In addition to being a general-purpose register, the ECX register is
used as an iteration counter for the loop (LOOP, LOOPE/LOOPZ,
LOOPNE/LOOPNZ, JECXZ) and the string (CMPSB/CMPSW/CMPSD,
LODSB/LODSW/LODSD, MOVSB/MOVSW/MOVSD, SCASB/SCASW/SCASD,
STOSB/STOSW/STOSD) instructions.
.*
.section The EDX Register
.*
.np
.ix 'registers' 'EDX'
.ix 'EDX register'
The EDX register is known as the data register.
It is used implicitly by the multiply and divide instructions.
The DX register (low-order 16 bits of the EDX register) can also be
used for the port address for the IN and OUT instructions.
.*
.section The ESP and EBP Registers
.*
.np
.ix 'registers' 'ESP'
.ix 'ESP register'
.ix 'registers' 'EBP'
.ix 'EBP register'
These registers use the stack segment (SS) during memory address
calculation.
Hence they can be used to access data which resides in the stack
segment.
The ESP register allows the implementation of a stack in memory and
hence it is referred to as the stack pointer.
Instructions such as PUSH and POP operate implicitly on this register.
The base pointer (EBP) can also be used to access data in the stack
segment.
This register is typically used to reference parameters and local
variables on the stack.
.*
.section The ESI and EDI Registers
.*
.np
.ix 'registers' 'ESI'
.ix 'ESI register'
.ix 'registers' 'EDI'
.ix 'EDI register'
The primary function of these registers is found in the string
instructions.
The data segment register (DS) in conjunction with the ESI register
form the source address of the string.
The extra segment register (ES) in conjunction with the EDI register
form the destination address for the string move.
.*
.endlevel
.*
.section Segment Registers
.*
.np
.ix 'registers' 'CS'
.ix 'registers' 'DS'
.ix 'registers' 'ES'
.ix 'registers' 'SS'
.ix 'registers' 'FS'
.ix 'registers' 'GS'
.ix 'CS register'
.ix 'DS register'
.ix 'ES register'
.ix 'SS register'
.ix 'FS register'
.ix 'GS register'
The 6 segment registers are named CS, DS, ES, SS, FS and GS.
Each segment register defines an address space of up to 4 gigabytes
(4GB).
Each instruction references a default segment register.
In most cases, these defaults can be overridden by specifying a
segment register with the operand.
:image depth='3.5i' file='386ARCH2' text='Segment Registers'.
.*
.beglevel
.*
.section The CS Register
.*
.np
.ix 'registers' 'CS'
.ix 'CS register'
The CS register is known as the code segment register.
The code segment register is used in conjunction with the
instruction pointer to determine the address of the instruction
to be executed.
.*
.section The DS Register
.*
.np
.ix 'registers' 'DS'
.ix 'DS register'
The DS register is known as the data segment register.
References
to data are relative to this register.
.*
.section The ES, FS and GS Registers
.*
.np
.ix 'registers' 'ES'
.ix 'ES register'
.ix 'registers' 'FS'
.ix 'FS register'
.ix 'registers' 'GS'
.ix 'GS register'
The ES, FS and GS registers are additional data segment registers.
The ES register is used in memory address calculations for the
destination of string operations.
.*
.section The SS Register
.*
.np
.ix 'registers' 'SS'
.ix 'SS register'
The SS register is known as the stack segment register.
The SS register is used in memory address calculations involving
the pointer registers EBP and ESP.
.*
.endlevel
.*
.section Instruction Pointer
.*
.np
.ix 'registers' 'EIP'
.ix 'EIP register'
The instruction pointer (EIP) is a 32-bit register which
defines the offset in the address space defined by the CS segment
register of the next instruction to be executed.
.*
.section Flags Register
.*
.np
.ix 'flags'
The flags register is a 32-bit register named EFLAGS which contains a
number of status bits.
This register is sometimes referred to as the status register.
Bits in this register are numbered from 0 to 31, where 0 is the least
significant bit and 31 is the most significant bit.
On the 386 only bits 0, 2, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 and
17 are defined.
The remaining bits are reserved.
The low-order 16 bits of EFLAGS is called FLAGS and can be treated as
a unit.
This is particularly useful when executing 8086 and 286 code since
this part of EFLAGS is identical to the FLAGS register of the 8086 and
286.
.np
Not all instructions change the state of the flags register.
You must look up the description of a particular instruction to see
what effect it might have, if any, on the flags register.
:image depth='1.5i' file='386ARCH3' text='Flags Register'.
.synote compact
.note VM
= Virtual 8086 Mode
.note RF
= Resume Flag
.note NT
= Nested Task Flag
.note IOPL
= I/O Privilege Level
.note OF
= Overflow Flag
.note DF
= Direction Flag
.note IF
= Interrupt Flag
.note TF
= Trace Flag
.note SF
= Sign Flag
.note ZF
= Zero Flag
.note AF
= Auxiliary Carry Flag
.note PF
= Parity Flag
.note CF
= Carry Flag
.esynote
.*
.beglevel
.*
.section The Virtual 8086 Mode
.*
.np
.ix 'flags' 'virtual 8086 mode'
.ix 'virtual 8086 mode'
This flag, when set, indicates that the task is executing an 8086
program.
.*
.section The Resume Flag
.*
.np
.ix 'flags' 'resume'
.ix 'resume flag'
This flag temporarily disables debug exceptions so that an instruction
can be restarted after a debug exception without immediately causing
another debug exception.
.*
.section The Nested Task Flag
.*
.np
.ix 'flags' 'nested task'
.ix 'nested task flag'
The processor uses this flag to control chaining of interrupted and called
tasks.