86arch.gml

开放源码的编译器open watcom 1.6.0版的源代码

.ix 'sign flag'
The Sign flag is bit 7 of the flags register and is referred
to as SF.
SF is set equal to the high-order bit of the result of a computation.
SF is set to 1 (TRUE) if the result is negative.
SF is set to 0 (FALSE) if the result is not negative.
.*
.section The Trap Flag
.*
.np
.ix 'flags' 'trap'
.ix 'trap flag'
The Trap flag is bit 8 of the flags register and is referred to as TF.
When set, TF causes the 8086 microprocessor to "single step".
Each instruction that is executed when TF is set results in a
software interrupt being generated.
This is useful in debugging when a trace of the instructions
executed is desired.
.*
.section The Interrupt Enable Flag
.*
.np
.ix 'flags' 'interrupt enable'
.ix 'interrupt enable flag'
The Interrupt Enable flag is bit 9 of the flags register and
is referred to as IF.
IF determines whether interrupt processing is enabled or disabled.
When IF is set to 1 (TRUE) interrupts are enabled; when IF is 0
(FALSE) interrupts are disabled.
The setting of IF can be controlled using the CLI and STI
instructions of the 8086.
.*
.section The Direction Flag
.*
.np
.ix 'flags' 'direction'
.ix 'direction flag'
The Direction flag is bit 10 of the flags register and is
referred to as DF.
DF determines whether string operations increment or decrement their
operands.
When DF is 1 (TRUE) the operands will be decremented; when DF is 0
(FALSE) the operands will be incremented.
The setting of DF is controlled by the CLD and STD instructions.
.*
.section The Overflow Flag
.*
.np
.ix 'flags' 'overflow'
.ix 'overflow flag'
The Overflow flag is bit 11 of the flags register and is referred to
as OF.
OF represents a magnitude overflow in signed binary arithmetic.
OF is set to 1 (TRUE) when the result of the computation exceeds 32767
(which means that the result is now negative) or is less than -32768
(which means that the result is now positive).
OF is set to 0 (FALSE) when the result of the computation did not
overflow.
.*
.endlevel
.*
.section Addressing Modes
.*
.np
.ix 'addressing modes'
All 8086 memory addresses are 20 bits wide, this allows an 8086
microprocessor to address a maximum of 1 Megabyte of memory.
The construction of a memory address consists of two parts,
effective address calculation and memory address calculation.
.*
.section Effective Address Calculation
.*
.np
.ix 'effective address'
Effective address calculation consists of instruction fetching
and data fetching.
Instruction fetching describes how flow of control is performed.
Data fetching describes how data can be referenced by a program.
.*
.beglevel
.*
.section Instruction Fetching
.*
.np
.ix 'instruction fetching'
.ix 'IP register'
The code segment register (CS) defines the instruction space from
which instructions can be fetched.
The offset of the next instruction to be fetched from the code
segment is contained in the instruction pointer register (IP).
After instruction fetch, the IP register is incremented by the
size of the instruction.
A jump or call instruction can cause the IP to change in three
additional ways.
.begnote
.point Instruction Pointer Relative
.ix 'instruction fetch' 'IP relative'
.ix 'IP relative instruction fetch'
The instruction contains an 8 or 16-bit displacement which is
added to the IP as a signed offset.
The next instruction to be fetched is found at this new address.
This is referred to as an intrasegment operation since it does
not result in the segment registers being changed.
.point Direct Addressing
.ix 'addressing' 'direct'
.ix 'direct addressing'
The instruction contains two 16-bit values which are loaded into
the IP and the CS register.
This causes an absolute jump or call to any location in the 8086
memory.
Since this operation results in a change to the segment register
as well as the IP, it is referred to as an intersegment
operation.
.point Indirect Addressing
.ix 'addressing' 'indirect'
.ix 'indirect addressing'
The memory address referenced by the instruction is either one or
two 16-bit values.
If a single 16-bit value exists, it is used to replace the value
in the IP.
If two 16-bit values exist, the first value replaces the IP and
the second replaces the CS register.
.endpoint
.*
.section Data Fetching
.*
.ix 'addressing modes' 'data'
.np
The 8086 has five data addressing modes.
These addressing modes are Base, Direct, Immediate, Indexed and
Base Indexed.
.*
.beglevel
.*
.section Base Addressing
.*
.np
.ix 'addressing' 'base'
.ix 'base addressing'
Base addressing uses the BX or BP register as a base register
for the address calculation.
The choice of which base register to use depends on which segment
register you wish to have used in the calculation.
The BX base register uses the DS segment register and the BP base
register uses the SS segment register.
The contents of the base register along with the segment register
identify a unique memory location.
Base addressing allows an 8 or 16-bit displacement to be
specified along with the base register.
If a displacement is specified, it is added to the contents of
the base register to determine the offset past the segment
register during address calculation.
If the displacement is 8 bits, it is sign extended to 16 bits
during the address calculation phase.
.*
.section Direct Addressing
.*
.np
.ix 'addressing' 'direct'
.ix 'direct addressing'
Direct addressing is the simplest addressing mode on the 8086.
The two bytes following the operation code byte contain an offset
which when combined with the data segment register (DS) define a
memory address.
.*
.section Immediate Addressing
.*
.np
.ix 'addressing' 'immediate'
.ix 'immediate addressing'
Immediate addressing implies that the data can be found in the
bytes following the instruction code in the instruction space
defined by the CS segment register.
This addressing mode is usually employed with program constants.
Depending on the instruction, the immediate value may be 8 or 16 bits
long.
If the constant is 16 bits long, the low-order 8 bits are stored
before the high-order 8 bits as is the case with all 16-bit data
entities on the 8086.
.*
.section Indexed Addressing
.*
.np
.ix 'addressing' 'indexed'
.ix 'indexed addressing'
Indexed addressing is performed by using the SI and DI index
registers.
The index registers can be used as pointers to data structures.
In this addressing mode, you can optionally specify an 8 or 16-bit
displacement which is added to the value in the index register to
determine the effective address.
If an 8-bit displacement is specified, the displacement is
converted to a 16-bit value by sign extension before the addition
is performed.
.*
.section Base Indexed Addressing
.*
.np
.ix 'addressing' 'base indexed'
.ix 'base indexed addressing'
Base indexed addressing is a combination of Base addressing and
Indexed addressing as described above.
The addressing mode allows a base register, an index register and
an optional displacement to be specified.
If BX is the base register, the default segment register used
during addressing is DS.
If BP is used, the default segment register is SS.
.*
.endlevel
.*
.endlevel
.keep 12
.*
.section Memory Address Calculation in Real Mode
.*
.np
.ix 'address calculation'
.ix 'real mode' 'address calculation'
Once a 16-bit effective address is computed, an 8086 memory address
is formed by summing the computed address with the contents of a
specified segment register.
.ix 'paragraph'
To form the 20-bit memory address, the 16-bit segment register is
shifted left 4 bit positions forming a 20-bit paragraph address.
A paragraph is defined to be a memory address which is a multiple
of sixteen.
The effective address, which was calculated as described above,
is then added to the 20-bit paragraph address forming a 20-bit
memory address.
Hence the 16-bit effective address is a byte offset from a
segment register.
.np
.ix 'address space'
The 4 segment registers on the 8086 allow four address spaces to
be selected at any time.
Since the effective address calculation determines a 16-bit
offset, each address space can be a maximum of 64K bytes.
The 8086 does not restrict the values which can be placed in a
segment register.
The segment registers define an origin of an address space which
may overlap with address spaces defined by other segment
registers.
.*
.if '&target' eq 'QNX' .do begin
.keep
.*
.section Memory Address Calculation in Protected Mode
.*
.np
.ix 'address calculation'
.ix 'protected mode' 'address calculation'
In protected mode, the 286, 386, etc. processors calculate the
effective address in a slightly different way than real mode.
In protected mode, the segment register value is simply an integer
value that is used to index a table in memory called the "Descriptor
Table".
This table contains entries called "descriptors".
Each entry contains the starting address of the corresponding segment.
The value in the descriptor is added to the offset to obtain the
effective address.
On the 286, the segment start address is 24 bits long.
Thus up to 16 megabytes (2**24) of memory can be addressed.
.np
The operating system is responsible for creating the descriptor table.
It will create one for each process in the system.
Some of the bits in the descriptor entry describe how memory
protection is set up.
The table will map out which areas of memory can be accessed by the
process, which are read/write, and which are read-only.
.do end