86arch.gml

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.chap 8086 Architecture
.*
.section Registers
.*
.np
.ix 'registers'
The register model for the 8086 microprocessor consists of 4
general purpose registers, 2 index registers, 2 pointer
registers, 4 segment registers, an instruction pointer and a
flags register.
Each of the registers is 16 bits wide.
.*
.section General Registers
.*
.np
.ix 'general registers'
The four general purpose 16-bit registers are named AX, BX, CX, and DX.
These registers can be used as 16-bit accumulators or they can each
be divided into 2 8-bit registers.
The eight-bit registers are named AH, AL, BH, BL, CH, CL, DH and DL.
:image depth='2.0i' file='86ARCH1' text='8086 Registers'.
.np
The general purpose registers can all be used as operands in the
arithmetic and logical instructions.
However, each register has specific functions as well.
.*
.beglevel
.*
.section The AX Register
.*
.np
.ix 'registers' 'AX'
.ix 'AX register'
The AX register is known as the accumulator.
Some arithmetic operations implicitly use this register.
For example, the multiply and divide instructions require the use
of the AX register.
The input/output instructions also use this register for
transferring data from input/output devices to the 8086
processor.
.*
.section The BX Register
.*
.np
.ix 'registers' 'BX'
.ix 'BX register'
The BX register is known as the base register.
The base register is the only general purpose register which can
be used in an address calculation.
The BX register can serve as the base address for any items in
the data segment.
.*
.section The CX Register
.*
.np
.ix 'registers' 'CX'
.ix 'CX register'
The CX register is known as the count register.
In addition to being a general purpose register, the CX register
is used as an iteration counter for the loop (LOOP, LOOPE/LOOPZ,
LOOPNE/LOOPNZ, JCXZ) and the string (CMPSB/CMPSW, LODSB/LODSW,
MOVB/MOVW, SCASB/SCASW, STOSB/STOSW) instructions.
.*
.section The DX Register
.*
.np
.ix 'registers' 'DX'
.ix 'DX register'
The DX register is known as the data register.
It is used implicitly by the word multiply and divide instructions.
This register is also used to specify the port address for the
input/output instructions.
Whenever an input/output port address is in the range 256 to 65535
the DX register must be used.
It is the only register that can perform this function.
.*
.endlevel
.*
.section Pointer Registers
.*
.np
.ix 'registers' 'SP'
.ix 'SP register'
.ix 'registers' 'BP'
.ix 'BP register'
The pointer registers are named SP and BP.
These registers use the stack segment (SS) during memory address
calculation.
Hence they can be used to access data which resides in the stack
segment.
The SP register allows the implementation of a stack in memory
and hence it is referred to as the stack pointer.
Instructions such as PUSH and POP operate implicitly on this register.
The base pointer (BP) can also be used to access data in the
stack segment.
This register is typically used to reference parameters and local
variables on the stack.
:image depth='1.1i' file='86ARCH2' text='SP/BP Registers'.
.*
.section Index Registers
.*
.np
.ix 'registers' 'SI'
.ix 'SI register'
.ix 'registers' 'DI'
.ix 'DI register'
The 8086 microprocessor has two index registers which can be
used to reference data in the data segment.
These two registers are the SI and DI registers.
Each of these registers is 16 bits wide and like the general
purpose registers can be used in arithmetic and logical
operations.
However, the primary function of these registers is found in the
string instructions.
The data segment register (DS) in conjunction with the SI
register form the source address of the string.
The extra segment register (ES) in conjunction with the DI
register form the destination address for the string move.
:image depth='1.1i' file='86ARCH3' text='SI/DI Index Registers'.
.*
.section Instruction Pointer
.*
.np
.ix 'registers' 'IP'
.ix 'IP register'
The instruction pointer (IP) is a 16-bit register which is
commonly referred to as the program counter.
The instruction pointer defines the offset in the address space
defined by the CS register of the next instruction to be
executed.
.*
.section Segment Registers
.*
.np
Physical memory addresses on the 8086 are 20 bits wide, hence we
require more than a 16-bit register to determine a unique
physical address.
The 8086 uses one of the four segment registers in all memory
address calculations to resolve this problem.
Each of the segment registers is 16 bits wide.
A physical address is determined by a 16-bit segment register and
a 16-bit offset as follows.
The contents of the segment register are multiplied by 16, then
the offset is added to form the physical address.
.np
.ix 'registers' 'CS'
.ix 'registers' 'DS'
.ix 'registers' 'ES'
.ix 'registers' 'SS'
.ix 'CS register'
.ix 'DS register'
.ix 'ES register'
.ix 'SS register'
The four segment registers are named CS, DS, ES, and SS.
Each segment register defines an address space of 65536 bytes
(64K).
Each instruction references a default segment register.
In most cases, these defaults can be overridden by specifying a
segment register with the operand.
:image depth='2.05i' file='86ARCH4' text='Segment Registers'.
.*
.beglevel
.*
.section The CS Register
.*
.np
.ix 'registers' 'CS'
.ix 'CS register'
The CS register is known as the code segment register.
The code segment register is used in conjunction with the
instruction pointer to determine the address of the instruction
to be executed.
.*
.section The DS Register
.*
.np
.ix 'registers' 'DS'
.ix 'DS register'
The DS register is known as the data segment register.
References
to data are relative to this register.
.*
.section The ES Register
.*
.np
.ix 'registers' 'ES'
.ix 'ES register'
The ES register is known as the extra segment register.
The ES register is used in memory address calculations for the
destination of string operations.
.*
.section The SS Register
.*
.np
.ix 'registers' 'SS'
.ix 'SS register'
The SS register is known as the stack segment register.
The SS register is used in memory address calculations involving
the pointer registers BP and SP.
.*
.endlevel
.*
.section Flags Register
.*
.np
.ix 'flags'
The flags register is a 16-bit register which contains a number
of status bits.
This register is sometimes referred to as the status register.
Bits in this register are numbered from 0 to 15, where 0 is the
least significant bit and 15 is the most significant bit.
On the 8086 only bits 0, 2, 4, 6, 7, 8, 9, 10, and 11 are
defined.
The remaining bits are reserved and are normally set to zero.
.np
Not all instructions change the state of the flags register.
You must look up the description of a particular instruction to
see what effect it might have, if any, on the flags register.
:image depth='2.73i' file='86ARCH5' text='Flags Register'.
.*
.beglevel
.*
.section The Carry Flag
.*
.np
.ix 'flags' 'carry'
.ix 'carry flag'
The Carry flag is bit 0 of the status register and is referred to as
CF.
CF reflects a carry out of the high bit following an arithmetic
operation.
CF is set to 1 (TRUE) when there is a carry.
CF is set to 0 (FALSE) when there is no carry.
.*
.section The Parity Flag
.*
.np
.ix 'flags' 'parity'
.ix 'parity flag'
The Parity flag is bit 2 of the flags register and is referred to
as PF.
PF is set to 1 (TRUE) when the resulting lower 8 bits of a data
operation has an even number of 1 bits.
An odd number of 1 bits results in the PF flag being set to 0 (FALSE).
.*
.section The Auxiliary Carry Flag
.*
.np
.ix 'flags' 'auxiliary carry'
.ix 'auxiliary carry flag'
The Auxiliary carry flag is bit 4 of the flags register and is
referred to as AF.
The AF flag represents a 4-bit (half-byte or nibble) carry, which is
a carry out of bit 3 in an 8-bit data item.
AF is set to 1 (TRUE) when there is a carry.
AF is set to 0 (FALSE) when there is no carry.
.*
.section The Zero Flag
.*
.np
.ix 'flags' 'zero'
.ix 'zero flag'
The Zero flag is bit 6 of the flags register and is referred to as ZF.
ZF is set to 1 (TRUE) when the result of the computation is zero.
ZF is set to 0 (FALSE) when the result of the computation is not
zero.
.*
.section The Sign Flag
.*
.np
.ix 'flags' 'sign'