pcscrnio.h
来自「开放源码的编译器open watcom 1.6.0版的源代码」· C头文件 代码 · 共 490 行 · 第 1/2 页
H
490 行
0XB7 0X00 /* mov bh,0 */ \
0XCD 0X10 /* int 10 */ \
0X5D /* pop bp */ \
0X07 /* pop es */ \
parm value [ cx ] modify [ ax bx dx ];
#pragma aux BIOSEGAChrSet = \
0X55 /* push bp */ \
0XB4 0X11 /* mov ah,11 */ \
0XB3 0X00 /* mov bl,0 */ \
0XCD 0X10 /* int 10 */ \
0X5D /* pop bp */ \
parm [ al ] modify [ ax bx ];
#pragma aux BIOSCharSet = \
0X87 0XF5 /* xchg bp,si */ \
0XB4 0X11 /* mov ah,11 */ \
0XB3 0X00 /* mov bl,0 */ \
0XCD 0X10 /* int 10 */ \
0X87 0XF5 /* xchg bp,si */ \
parm [ al ] [ bh ] [ cx ] [ dx ] [ es ] [ si ] modify [ ax bx cx dx ];
enum ega_seqencer {
SEQ_PORT = 0x3c4,
SEQ_RESET = 0,
SEQ_CLOCK_MODE = 1,
SEQ_MAP_MASK = 2,
SEQ_CHAR_MAP_SEL= 3,
SEQ_MEM_MODE = 4,
/* reset register */
RES_NOT_ASYNCH = 0x01,
RES_NOT_SYNCH = 0x02,
/* clock mode register */
CLK_8_DOTS = 0x01,
CLK_SHIFT_LOAD = 0x04,
CLK_DOT_CLOCK = 0x08,
/* map mask register */
MSK_MAP_0 = 0x01,
MSK_MAP_1 = 0x02,
MSK_MAP_2 = 0x04,
MSK_MAP_3 = 0x08,
/* character map register */
CHR_MAPA_0 = 0x00,
CHR_MAPA_1 = 0x01,
CHR_MAPA_2 = 0x02,
CHR_MAPA_3 = 0x03,
CHR_MAPB_0 = 0x00,
CHR_MAPB_1 = 0x04,
CHR_MAPB_2 = 0x08,
CHR_MAPB_3 = 0x0c,
/* memory mode register */
MEM_ALPHA = 0x01,
MEM_EXTENDED = 0x02,
MEM_NOT_ODD_EVEN= 0x04
};
enum ega_graphics_controller {
GRA_PORT = 0x3ce,
GRA_SET_RESET = 0,
GRA_ENABLE_SR = 1,
GRA_COLOR_COMP = 2,
GRA_DATA_ROT = 3,
GRA_READ_MAP = 4,
GRA_GRAPH_MODE = 5,
GRA_MISC = 6,
GRA_COLOR_CARE = 7,
GRA_BIT_MASK = 8,
/* set/reset register */
SR_MAP_0 = 0x01,
SR_MAP_1 = 0x02,
SR_MAP_2 = 0x04,
SR_MAP_3 = 0x08,
/* enable set/reset register */
ESR_MAP_0 = 0x01,
ESR_MAP_1 = 0x02,
ESR_MAP_2 = 0x04,
ESR_MAP_3 = 0x08,
/* colour compare register */
COL_MAP_0 = 0x01,
COL_MAP_1 = 0x02,
COL_MAP_2 = 0x04,
COL_MAP_3 = 0x08,
/* data rotate register */
/* bottom three bits are the right rotate count */
ROT_UNMOD = 0x00,
ROT_AND = 0x08,
ROT_OR = 0x10,
ROT_XOR = 0x18,
/* read map select register */
RMS_MAP_0 = 0x00,
RMS_MAP_1 = 0x01,
RMS_MAP_2 = 0x02,
RMS_MAP_3 = 0x03,
/* graphics mode register */
GRM_EN_ROT = 0x00,
GRM_SYS_LATCH = 0x01,
GRM_BIT_PLANE = 0x02,
GRM_ILL = 0x03,
GRM_TEST = 0x04,
GRM_READ_MODE = 0x08,
GRM_ODD_EVEN = 0x10,
GRM_SHIFT = 0x20,
/* miscellaneous register */
MIS_GRAPH_MODE = 0x01,
MIS_CHAIN = 0x02,
MIS_A000_128 = 0x00,
MIS_A000_64 = 0x04,
MIS_B000_32 = 0x08,
MIS_B800_32 = 0x0c,
/* colour don't care register */
CDC_CARE_MAP_0 = 0x01,
CDC_CARE_MAP_1 = 0x02,
CDC_CARE_MAP_2 = 0x04,
CDC_CARE_MAP_3 = 0x08
/* bit mask register */
/* bit N set to one causes that bit in each plane not to be written */
};
#pragma aux _ega_write = /* write ega/vga registers */ \
0xef /* out dx,ax */ \
parm [dx] [al] [ah] \
modify exact [];
#pragma aux _vga_read = /* read vga registers */ \
0xee /* out dx,al */ \
0x42 /* inc dx */ \
0xec /* in al,dx */ \
parm [dx] [al] \
value [al];
#define _seq_write( reg, val ) _ega_write( SEQ_PORT, reg, val )
#define _graph_write( reg, val ) _ega_write( GRA_PORT, reg, val )
#define _seq_read( reg ) _vga_read( SEQ_PORT, reg )
#define _graph_read( reg ) _vga_read( GRA_PORT, reg )
#pragma aux _disablev = /* disable video */ \
0xec /* in al,dx */ \
0xa8 0x08 /* test al,8 */ \
0x74 0xfb /* jz -5 */ \
0xba 0xc0 0x03 /* mov dx,03c0 */ \
0xb0 0x11 /* mov al,11 */ \
0xee /* out dx,al */ \
0xb0 0x00 /* mov al,0 */ \
0xee /* out dx,al */ \
parm [dx] \
modify [ax dx];
#pragma aux _enablev = /* enable video */ \
0xec /* in al,dx */ \
0xa8 0x08 /* test al,8 */ \
0x74 0xfb /* jz -5 */ \
0xba 0xc0 0x03 /* mov dx,03c0 */ \
0xb0 0x31 /* mov al,31 */ \
0xee /* out dx,al */ \
0xb0 0x00 /* mov al,0 */ \
0xee /* out dx,al */ \
parm [dx] \
modify [ax dx];
enum vid_state_info {
VID_STATE_HARDWARE = 0x1,
VID_STATE_BIOS = 0x2,
VID_STATE_DAC_N_COLOURS = 0x4,
VID_STATE_ALL = 0x7
};
#pragma aux _vidstatesize = /* get video save size */ \
0xb8 0x00 0x1c /* mov ax,1c00 */ \
0xcd 0x10 /* int 10 */ \
0x3c 0x1c /* cmp al,1c */ \
0x74 0x02 /* je $+2 */ \
0x31 0xdb /* xor bx,bx */ \
parm [cx] \
value [bx] \
modify exact [ax bx];
#pragma aux _vidstatesave = /* save video state */ \
0xb8 0x01 0x1c /* mov ax,1c01 */ \
0xcd 0x10 /* int 10 */ \
parm [cx] [es] [bx] \
modify exact [ax];
#pragma aux _vidstaterestore = /* restore video state */ \
0xb8 0x02 0x1c /* mov ax,1c02 */ \
0xcd 0x10 /* int 10 */ \
parm [cx] [es] [bx] \
modify exact [ax];
#pragma aux Fillb = \
/* Fillb( toseg, tooff, val, len ); */ \
0XF3 /* rep */ \
0XAA /* stosb */ \
parm caller [ es ] [ di ] [ ax ] [ cx ] \
modify [ di es ];
#define VIDMONOINDXREG 0X03B4
#define VIDCOLRINDXREG 0X03D4
extern char BIOSGetMode();
extern int BIOSGetPage();
extern signed long BIOSEGAInfo();
extern void BIOSSetPage();
extern void BIOSSetMode();
extern void BIOSEGAChrSet();
extern void BIOSEGALoadChrSet();
extern int BIOSGetCurPos();
extern void BIOSSetCurPos();
extern int BIOSGetCurTyp();
extern void BIOSSetCurTyp();
extern char BIOSGetRows();
extern unsigned BIOSGetPoints();
extern char BIOSGetAttr();
extern void BIOSSetAttr( unsigned char );
extern void BIOSCharSet();
extern char VIDGetCol();
extern char VIDGetRow();
extern void VIDWait();
extern void VIDSetPos();
extern void VIDSetRow();
extern void VIDSetCol();
extern void VIDSetCurTyp();
extern unsigned VIDGetCurTyp();
extern void Fillb( unsigned, unsigned, unsigned, unsigned );
extern void _ega_write( unsigned, char, char );
extern char _vga_read( unsigned, char );
extern void _disablev( unsigned );
extern void _enablev( unsigned );
extern unsigned _vidstatesize( unsigned );
extern void _vidstatesave( unsigned, unsigned, unsigned );
extern void _vidstaterestore( unsigned, unsigned, unsigned );
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