i86table.c
来自「开放源码的编译器open watcom 1.6.0版的源代码」· C语言 代码 · 共 1,444 行 · 第 1/5 页
C
1,444 行
static opcode_entry Mod1[] = {
/************************/
/* op1 op2 res eq verify gen reg fu*/
{_Bin( ANY, C, ANY, NONE ), V_NO, R_MOVOP2TEMP, RG_BYTE_MOD,FU_NO},
{_Bin( R, R, R, NONE ), V_NO, G_R2, RG_BYTE_MOD,FU_IDIV},
{_Bin( R, M, R, NONE ), V_NO, G_M2, RG_BYTE_MOD,FU_IDIV},
{_Bin( R, U|M, R, NONE ), V_DIV_BUG, R_LOADOP2, RG_BYTE_MOD,FU_NO},
{_Bin( R, U, R, NONE ), V_NO, G_UNKNOWN, RG_BYTE_MOD,FU_NO},
{_Bin( ANY, ANY, ANY, NONE ), V_NO, R_DIVREGISTER,RG_BYTE_MOD,FU_NO},
};
static opcode_entry Mod2[] = {
/************************/
/* op1 op2 res eq verify gen reg fu*/
// _Bin( R, C, R, NONE ), V_OP2ONE, R_SAVEFACE, RG_WORD_MOD,FU_NO},
{_Bin( ANY, C, ANY, NONE ), V_NO, R_MOVOP2TEMP, RG_WORD_MOD,FU_NO},
{_Bin( R, R, R, NONE ), V_NO, G_R2, RG_WORD_MOD,FU_IDIV},
{_Bin( R, M, R, NONE ), V_NO, G_M2, RG_WORD_MOD,FU_IDIV},
{_Bin( R, U|M, R, NONE ), V_DIV_BUG, R_LOADOP2, RG_WORD_MOD,FU_NO},
{_Bin( R, U, R, NONE ), V_NO, G_UNKNOWN, RG_WORD_MOD,FU_NO},
{_Bin( ANY, ANY, ANY, NONE ), V_NO, R_DIVREGISTER,RG_WORD_MOD,FU_NO},
};
static opcode_entry Shft1[] = {
/*************************/
/* op1 op2 res eq verify gen reg fu*/
/* optimizing reductions*/
{_Bin( ANY, C, ANY, NONE ),V_OP2NEG, R_CHANGESHIFT,RG_BYTE_SHIFT,FU_NO},
{_Bin( ANY, C, ANY, NONE ),NVI(V_OP2ZERO),R_MAKEMOVE,RG_BYTE,FU_NO},
{_Bin( ANY, C, ANY, NONE ),V_SHIFT2BIG,R_FIXSHIFT, RG_BYTE_SHIFT,FU_NO},
/* instructions we can generate*/
{_Bin( C, C, ANY, EQ_R1 ),V_NO, R_MOVOP1TEMP, RG_BYTE,FU_NO},
{_Bin( R, C, R, EQ_R1 ),V_LSHONE, R_ADDRR, RG_BYTE,FU_NO},
{_Bin( R, C, R, EQ_R1 ),V_OP2ONE, G_R1SHIFT, RG_BYTE,FU_ALU1},
{_Bin( M, C, M, EQ_R1 ),V_OP2ONE, G_1SHIFT, RG_,FU_ALU1},
{_Bin( R, C, R, EQ_R1 ),V_80186, G_RNSHIFT, RG_BYTE,FU_ALU1},
{_Bin( M, C, M, EQ_R1 ),V_80186, G_NSHIFT, RG_,FU_ALU1},
{_Bin( R, C, R, EQ_R1 ),V_OP2TWO, R_DOUBLEHALF, RG_BYTE,FU_NO},
{_Bin( M, C, M, EQ_R1 ),V_OP2TWO, R_DOUBLEHALF, RG_,FU_NO},
{_Bin( R, R, R, EQ_R1 ),V_NO, G_RCLSHIFT, RG_BYTE_SHIFT,FU_ALU1},
{_Bin( M, R, M, EQ_R1 ),V_NO, G_CLSHIFT, RG_BYTE_SHIFT,FU_ALU1},
/* simplifying reductions*/
{_Bin( R|M|C,C, R|M, NONE ), V_80186, R_OP1RESTEMP,RG_BYTE_SHIFT,FU_NO},
{_Bin( R|M|C,C, R|M, NONE ), V_OP2ONE, R_OP1RESTEMP,RG_BYTE_SHIFT,FU_NO},
{_Bin( R|M|C,C, R|M, NONE ), V_OP2TWO, R_OP1RESTEMP,RG_BYTE_SHIFT,FU_NO},
{_Bin( R|M|C,R, R|M, NONE ), V_NO, R_OP1RESTEMP,RG_BYTE_SHIFT,FU_NO},
{_Bin( ANY, C, ANY, EQ_R1), V_OP2ONE, G_UNKNOWN, RG_BYTE,FU_NO},
{_Bin( ANY, C, ANY, NONE ), V_OP2ONE, G_UNKNOWN, RG_BYTE_NEED,FU_NO},
{_Bin( ANY, C, ANY, EQ_R1), V_OP2TWO, G_UNKNOWN, RG_BYTE,FU_NO},
{_Bin( ANY, C, ANY, NONE ), V_OP2TWO, G_UNKNOWN, RG_BYTE_NEED,FU_NO},
{_Bin( ANY, C, ANY, EQ_R1), V_80186, G_UNKNOWN, RG_BYTE,FU_NO},
{_Bin( ANY, C, ANY, NONE ), V_80186, G_UNKNOWN, RG_BYTE_NEED,FU_NO},
{_Bin( ANY, R, ANY, EQ_R1), V_NO, G_UNKNOWN, RG_BYTE_SHIFT,FU_NO},
{_Bin( ANY, R, ANY, NONE ), V_NO, G_UNKNOWN, RG_BYTE_SHIFT_NEED,FU_NO},
{_Bin( ANY, ANY, ANY, NONE ), V_NO, R_OP2CL, RG_,FU_NO},
};
static opcode_entry Shft2[] = {
/*************************/
/* op1 op2 res eq verify gen reg fu*/
/* optimizing reductions*/
{_Bin( ANY, C, ANY, NONE ),V_OP2NEG, R_CHANGESHIFT,RG_WORD_SHIFT,FU_NO},
{_Bin( ANY, C, ANY, NONE ),NVI(V_OP2ZERO),R_MAKEMOVE,RG_WORD,FU_NO},
{_Bin( ANY, C, ANY, NONE ),V_SHIFT2BIG,R_FIXSHIFT, RG_WORD_SHIFT,FU_NO},
{_Bin( R, C, R, NONE ),NVI(V_CYP2SHIFT),R_CYPSHIFT,RG_TWOBYTE,FU_NO},
{_Bin( M|U, C, M|U, NONE ),NVI(V_CYP2SHIFT),R_CYPSHIFT,RG_WORD,FU_NO},
/* instructions we can generate*/
{_Bin( C, C, ANY, EQ_R1 ),V_NO, R_MOVOP1TEMP, RG_WORD,FU_NO},
{_Bin( R, C, R, EQ_R1 ),V_LSHONE, R_ADDRR, RG_WORD,FU_NO},
{_Bin( R, C, R, EQ_R1 ),V_OP2ONE, G_R1SHIFT, RG_WORD,FU_ALU1},
{_Bin( M, C, M, EQ_R1 ),V_OP2ONE, G_1SHIFT, RG_,FU_ALU1},
{_Bin( R, C, R, EQ_R1 ),V_80186, G_RNSHIFT, RG_WORD,FU_ALU1},
{_Bin( M, C, M, EQ_R1 ),V_80186, G_NSHIFT, RG_,FU_ALU1},
{_Bin( R, C, R, EQ_R1 ),V_OP2TWO, R_DOUBLEHALF, RG_WORD,FU_NO},
{_Bin( M, C, M, EQ_R1 ),V_OP2TWO, R_DOUBLEHALF, RG_,FU_NO},
{_Bin( R, R, R, EQ_R1 ),V_NO, G_RCLSHIFT, RG_WORD_SHIFT,FU_ALU1},
{_Bin( M, R, M, EQ_R1 ),V_NO, G_CLSHIFT, RG_WORD_SHIFT,FU_ALU1},
/* simplifying reductions*/
{_Bin( R|M|C,C, R|M, NONE ), V_80186, R_OP1RESTEMP,RG_WORD_SHIFT,FU_NO},
{_Bin( R|M|C,C, R|M, NONE ), V_OP2ONE, R_OP1RESTEMP,RG_WORD_SHIFT,FU_NO},
{_Bin( R|M|C,C, R|M, NONE ), V_OP2TWO, R_OP1RESTEMP,RG_WORD_SHIFT,FU_NO},
{_Bin( R|M|C,R, R|M, NONE ), V_NO, R_OP1RESTEMP,RG_WORD_SHIFT,FU_NO},
{_Bin( ANY, C, ANY, EQ_R1), V_OP2ONE, G_UNKNOWN, RG_WORD,FU_NO},
{_Bin( ANY, C, ANY, NONE ), V_OP2ONE, G_UNKNOWN, RG_WORD_NEED,FU_NO},
{_Bin( ANY, C, ANY, EQ_R1), V_OP2TWO, G_UNKNOWN, RG_WORD,FU_NO},
{_Bin( ANY, C, ANY, NONE ), V_OP2TWO, G_UNKNOWN, RG_WORD_NEED,FU_NO},
{_Bin( ANY, C, ANY, EQ_R1), V_80186, G_UNKNOWN, RG_WORD,FU_NO},
{_Bin( ANY, C, ANY, NONE ), V_80186, G_UNKNOWN, RG_WORD_NEED,FU_NO},
{_Bin( ANY, R, ANY, EQ_R1), V_NO, G_UNKNOWN, RG_WORD_SHIFT,FU_NO},
{_Bin( ANY, R, ANY, NONE ), V_NO, G_UNKNOWN, RG_WORD_SHIFT_NEED,FU_NO},
{_Bin( ANY, ANY, ANY, NONE ), V_NO, R_OP2CL, RG_,FU_NO},
};
/**/
/* NEVER, NEVER touch this table unless you are feeling VERY brave (j.d)*/
static opcode_entry Shft4[] = {
/*************************/
/* op1 op2 res eq verify gen reg fu*/
/* optimizing reductions*/
{_Bin( ANY, C, ANY, NONE ),V_OP2NEG, R_CHANGESHIFT,RG_DBL_SHIFT,FU_NO},
{_Bin( ANY, C, ANY, NONE ),NVI(V_OP2ZERO), R_MAKEMOVE, RG_DOUBLE,FU_NO},
{_Bin( ANY, C, ANY, NONE ),NVI(V_CYP4SHIFT),R_CYPSHIFT, RG_DOUBLE,FU_NO},
/* instructions we can generate*/
{_Bin( C, C, ANY, EQ_R1 ),V_NO, R_MOVOP1TEMP, RG_DOUBLE,FU_NO},
{_Bin( R, C, R, EQ_R1 ),V_LSHONE, R_ADDRR, RG_DOUBLE,FU_NO},
{_Bin( R, C, R, EQ_R1 ),V_OP2ONE, G_4RSHIFT, RG_DOUBLE,FU_ALU1},
{_Bin( M, C, M, EQ_R1 ),V_OP2ONE, G_4SHIFT, RG_,FU_ALU1},
{_Bin( R, C, R, EQ_R1 ),V_OP2TWO, R_DOUBLEHALF, RG_DOUBLE,FU_NO},
{_Bin( M, C, M, EQ_R1 ),V_OP2TWO, R_DOUBLEHALF, RG_,FU_NO},
{_Bin( R, R, R, EQ_R1 ),V_NO, G_RCXSHIFT, RG_DBL_SHIFT,FU_ALU1},
{_Bin( R, C, R, EQ_R1 ),V_NO, G_RCXSHIFT, RG_DBL_SHIFT_NEED,FU_ALU1},
{_Bin( M, R, M, EQ_R1 ),V_NO, G_CXSHIFT, RG_DBL_SHIFT,FU_ALU1},
{_Bin( M, C, M, EQ_R1 ),V_NO, G_CXSHIFT, RG_DBL_SHIFT_NEED,FU_ALU1},
/* simplifying reductions*/
{_Bin( R, C, R, NONE ),V_BYTESHIFT,R_BYTESHIFT, RG_DBL_SHIFT,FU_NO},
{_Bin( R, C, M, NONE ),V_BYTESHIFT,R_BYTESHIFT, RG_DBL_SHIFT,FU_NO},
{_Bin( M, C, R, NONE ),V_BYTESHIFT,R_BYTESHIFT, RG_DBL_SHIFT,FU_NO},
{_Bin( ANY, C, ANY, EQ_R1 ), V_OP2ONE, G_UNKNOWN, RG_DOUBLE_NEED,FU_NO},
{_Bin( ANY, C, ANY, EQ_R1 ), V_OP2TWO, G_UNKNOWN, RG_DOUBLE_NEED,FU_NO},
{_Bin( ANY, R, ANY, EQ_R1 ), V_NO, G_UNKNOWN, RG_DBL_SHIFT,FU_NO},
{_Bin( ANY, C, ANY, EQ_R1 ), V_NO, G_UNKNOWN, RG_DBL_SHIFT_NEED,FU_NO},
{_Bin( ANY, ANY, ANY, EQ_R1 ), V_NO, R_OP2CX, RG_,FU_NO},
{_Bin( ANY, ANY, ANY, NONE ), V_NO, R_OP1RESTEMP,RG_DBL_SHIFT,FU_NO},
};
static opcode_entry TestOrCmp1[] = {
/******************************/
/* op1 op2 verify gen reg fu*/
{_Bin( C, C, ANY, EQ_R1 ),V_NO, R_MOVOP1TEMP, RG_DOUBLE,FU_NO},
{_Side( R, U ), V_CONSTTEMP, R_TEMP2CONST, RG_BYTE,FU_NO},
{_Side( U, R ), V_CONSTTEMP, R_TEMP2CONST, RG_BYTE,FU_NO},
{_Side( ANY, ANY ), NVI(V_CMPTRUE), R_CMPTRUE, RG_,FU_NO},
{_Side( ANY, ANY ), NVI(V_CMPFALSE),R_CMPFALSE, RG_,FU_NO},
/* instructions we can generate*/
{_SidCC( R, R ), V_NO, G_RR2, RG_BYTE,FU_ALU1},
{_SidCC( R, M ), V_NO, G_RM2, RG_BYTE,FU_ALU1},
{_SidCC( R, C ), V_OP2ZERO, G_TEST, RG_BYTE,FU_ALU1},
{_SidCC( R, C ), V_NO, G_AC, RG_BYTE_ACC,FU_ALU1},
{_SidCC( R, C ), V_NO, G_RC, RG_BYTE,FU_ALU1},
{_SidCC( M, C ), V_NO, G_MC, RG_,FU_ALU1},
/* simplifying reductions*/
{_Side( C, C ), V_NO, R_MOVOP1REG, RG_BYTE,FU_NO},
{_Side( C, ANY ), V_NO, R_SWAPCMP, RG_BYTE,FU_NO},
{_Side( M, R ), V_NO, R_SWAPCMP, RG_BYTE,FU_NO},
{_Side( M, M ), V_NO, R_MOVOP1REG, RG_BYTE,FU_NO},
{_Side( ANY, R|C ), V_NO, G_UNKNOWN, RG_BYTE,FU_NO},
{_Side( R|C, ANY ), V_NO, G_UNKNOWN, RG_BYTE,FU_NO},
{_Side( ANY, ANY ), V_NO, G_UNKNOWN, RG_BYTE_NEED,FU_NO},
};
static opcode_entry Test2[] = {
/*************************/
/* op1 op2 verify gen reg fu*/
/* optimizing reductions*/
{_Side( R|M|U,C ), NVI(V_OP2LOW_B_ZERO),R_CYPHIGH,RG_TWOBYTE,FU_NO},
{_Side( R|M|U,C ), NVI(V_OP2HIGH_B_ZERO),R_CYPLOW,RG_TWOBYTE,FU_NO},
{_Side( R, U ), V_CONSTTEMP, R_TEMP2CONST, RG_WORD,FU_NO},
{_Side( U, R ), V_CONSTTEMP, R_TEMP2CONST, RG_WORD,FU_NO},
{_Side( ANY, C ), V_CMPTRUE, R_CMPTRUE, RG_,FU_NO},
{_Side( ANY, C ), V_CMPFALSE, R_CMPFALSE, RG_,FU_NO},
/* instructions we can generate*/
{_SidCC( R, R ), V_NO, G_RR2, RG_WORD,FU_ALU1},
{_SidCC( R, M ), V_NO, G_RM2, RG_WORD,FU_ALU1},
{_SidCC( R, C ), V_NO, G_AC, RG_WORD_ACC,FU_ALU1},
{_SidCC( R, C ), V_NO, G_RC, RG_WORD,FU_ALU1},
{_SidCC( M, C ), V_NO, G_MC, RG_,FU_ALU1},
/* simplifying reductions*/
{_Side( C, C ), V_NO, R_MOVOP1REG, RG_WORD,FU_NO},
{_Side( C, ANY ), V_NO, R_SWAPCMP, RG_WORD,FU_NO},
{_Side( M, R ), V_NO, R_SWAPCMP, RG_WORD,FU_NO},
{_Side( M, M ), V_NO, R_MOVOP1REG, RG_WORD,FU_NO},
{_Side( ANY, R|C ), V_NO, G_UNKNOWN, RG_WORD,FU_NO},
{_Side( R|C, ANY ), V_NO, G_UNKNOWN, RG_WORD,FU_NO},
{_Side( ANY, ANY ), V_NO, G_UNKNOWN, RG_WORD_NEED,FU_NO},
};
static opcode_entry Test4[] = {
/*************************/
/* op1 op2 verify gen reg fu*/
{_Side( ANY, C ), NVI(V_OP2LOW_W_ZERO),R_CYPHIGH, RG_,FU_NO},
{_Side( ANY, C ), NVI(V_OP2HIGH_W_ZERO),R_CYPLOW, RG_,FU_NO},
{_Side( C, R|M|U ), V_NO, R_SWAPCMP, RG_,FU_NO},
{_Side( ANY, ANY ), V_NO, R_SPLITCMP, RG_,FU_NO},
};
static opcode_entry Test8[] = {
/*************************/
/* op1 op2 verify gen reg fu*/
{_Side( C, R|M|U ), V_NO, R_SWAPCMP, RG_,FU_NO},
{_Side( ANY, ANY ), V_NO, R_SPLIT8TST, RG_8,FU_NO},
};
static opcode_entry Cmp2[] = {
/************************/
/* op1 op2 verify gen reg fu*/
{_Side( R, U ), V_CONSTTEMP, R_TEMP2CONST, RG_WORD,FU_NO},
{_Side( U, R ), V_CONSTTEMP, R_TEMP2CONST, RG_WORD,FU_NO},
{_Side( ANY, ANY ), NVI(V_CMPTRUE), R_CMPTRUE, RG_,FU_NO},
{_Side( ANY, ANY ), NVI(V_CMPFALSE),R_CMPFALSE, RG_,FU_NO},
/* instructions we can generate*/
{_SidCC( R, C ), V_OP2ZERO, G_TEST, RG_WORD,FU_ALU1},
{_SidCC( R, R ), V_NO, G_RR2, RG_WORD,FU_ALU1},
{_SidCC( R, M ), V_NO, G_RM2, RG_WORD,FU_ALU1},
{_SidCC( R, C ), V_NO, G_AC, RG_WORD_ACC,FU_ALU1},
{_SidCC( R, C ), V_NO, G_RC, RG_WORD,FU_ALU1},
{_SidCC( M, C ), V_NO, G_MC, RG_,FU_ALU1},
/* simplifying reductions*/
{_Side( ANY, R ), V_NO, R_MOVOP2TEMP, RG_SEG_SEG,FU_NO},
{_Side( R, ANY ), V_NO, R_MOVOP1TEMP, RG_SEG_SEG,FU_NO},
{_Side( C, C ), V_NO, R_MOVOP1REG, RG_WORD,FU_NO},
{_Side( C, ANY ), V_NO, R_SWAPCMP, RG_WORD,FU_NO},
{_Side( M, R ), V_NO, R_SWAPCMP, RG_WORD,FU_NO},
{_Side( M, M ), V_NO, R_MOVOP1REG, RG_WORD,FU_NO},
{_Side( ANY, R|C ), V_NO, G_UNKNOWN, RG_WORD,FU_NO},
{_Side( R|C, ANY ), V_NO, G_UNKNOWN, RG_WORD,FU_NO},
{_Side( ANY, ANY ), V_NO, G_UNKNOWN, RG_WORD_NEED,FU_NO},
};
static opcode_entry Cmp4[] = {
/************************/
/* op1 op2 verify gen reg fu*/
// 2006-06-01 RomanT: It's not effective. Compare is DoNothing()'ed and
// operands are stuck unsplit, poisoning all analysis.
// {_Side( ANY, C ), V_CMPTRUE, R_CMPTRUE, RG_,FU_NO},
// {_Side( ANY, C ), V_CMPFALSE, R_CMPFALSE, RG_,FU_NO},
{_Side( ANY, C ), V_U_TEST, R_U_TEST, RG_DOUBLE,FU_NO},
{_Side( C, R|M|U ), V_NO, R_SWAPCMP, RG_DOUBLE,FU_NO},
{_Side( ANY, ANY ), V_NO, R_SPLITCMP, RG_DOUBLE,FU_NO},
};
static opcode_entry Cmp8[] = {
/************************/
/* op1 op2 verify gen reg fu*/
{_Side( C, R|M|U ), V_NO, R_SWAPCMP, RG_,FU_NO},
{_Side( ANY, ANY ), V_NO, R_SPLIT8CMP, RG_8,FU_NO},
};
static opcode_entry CmpFS[] = {
/*************************/
/* op1 op2 verify gen reg fu*/
{_Side( ANY, C ), V_OP2ZERO, R_HIGHCMP, RG_DBL_OR_PTR,FU_NO},
{_Side( ANY, C ), V_NO, R_FSCONSCMP, RG_DBL_OR_PTR,FU_NO},
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?