otsdiv.asm
来自「开放源码的编译器open watcom 1.6.0版的源代码」· 汇编 代码 · 共 634 行 · 第 1/2 页
ASM
634 行
beq $t0,d64_easy
inswl $a2,6,$a2
blt $t0,d64_sub
umulh $t0,$a2,$t0
ldq $t12,0x8($t12)
br d64_cont
d64_sub:
umulh $t0,$a2,$t0
ldq $t12,0x8($t12)
s4addq $a2,0,$a2
subq $t12,$a2,$t12
d64_cont:
s4addq $t0,$t12,$a2
umulh $a2,$a1,$t0
addq $t0,$a1,$t0
negq $t0,$t0
umulh $a2,$t0,$t12
cmovlt $t0,0,$a2
addq $a2,$t0,$t0
addq $t12,$t0,$a2
umulh $a2,$a1,$t0
addq $t0,$a1,$t0
negq $t0,$t0
umulh $a2,$t0,$t12
cmovlt $t0,0,$a2
addq $a2,$t0,$t0
addq $t12,$t0,$t0
umulh $t0,$a0,$a2
srl $a1,$v0,$a1
negq $v0,$v0
subq $v0,8,$v0
addq $a2,$a0,$a2
cmpult $a2,$a0,$t0
srl $a2,8,$a2
sll $t0,0x38,$t0
addq $t0,$a2,$t0
srl $t0,$v0,$v0
mulq $a1,$v0,$t0
subq $a0,$t0,$t0
cmpule $a1,$t0,$a2
subq $t0,$a1,$t12
cmovne $a2,$t12,$t0
addq $v0,$a2,$v0
ret $zero,($at)
d64_easy:
ldq $t0,0x8($t12)
srl $a1,$v0,$a1
blt $a2,d64_pow2
umulh $t0,$a0,$a2
negq $v0,$v0
and $a0,0xff,$t0
subq $v0,8,$v0
srl $a0,8,$t12
addq $a2,$t0,$t0
srl $t0,8,$t0
addq $t0,$t12,$t0
srl $t0,$v0,$v0
mulq $a1,$v0,$t0
subq $a0,$t0,$t0
ret $zero,($at)
d64_pow2:
not $v0,$v0
subq $a1,1,$t0
srl $a0,$v0,$v0
and $a0,$t0,$t0
ret $zero,($at)
d64end:
mov $a0,$t0
ret $zero,($at)
_OtsDivide64Overflow:
ldah $t12,h^_OtsDivData($zero)
lda $t12,l^_OtsDivData($t12)
not $a1,$t0
bne $t0,dl_skip
subq/v $zero,$a0,$v0
ret $zero,($ra)
nop
_OtsDivide64:
ldah $t12,h^_OtsDivData($zero)
lda $t12,l^_OtsDivData($t12)
dl_skip:
xor $a0,$a1,$a3
dl_retry:
lda $at,-0x200($a1)
ble $a1,dl_notpos
addq $a1,$a1,$v0
negq $a0,$a2
bgt $at,dl_lrgdiv
s8addq $v0,$t12,$t12
srl $a0,33,$t0
cmpule $a1,$a2,$v0
bne $t0,dl_64bit
cmovge $a0,$a0,$a2
beq $v0,dl_end
ldq $t12,($t12)
sra $a3,63,$a3
blt $t12,dl_smpwr2
umulh $a2,$t12,$v0
beq $a3,dl_end
negq $v0,$v0
ret $zero,($ra)
dl_64bit:
cmovge $a0,$a0,$a2
beq $v0,dl_end
ldq $t0,0x8($t12)
sra $a3,63,$a3
ldq $t12,($t12)
beq $t0,dl_smpwr2
umulh $a2,$t0,$v0
addq $v0,$a2,$a2
dl_smpwr2:
srl $a2,$t12,$a2
xor $a2,$a3,$a2
subq $a2,$a3,$v0
dl_end:
ret $zero,($ra)
dl_notpos:
beq $a1,divzer
subq $zero,$a1,$a1
subq $zero,$a0,$a0
bgt $a1,dl_retry
cmpeq $a0,$a1,$v0
ret $zero,($ra)
dl_lrgdiv:
sra $a3,63,$a3
cmovlt $a0,$a2,$a0
bsr $at,div64
xor $v0,$a3,$v0
subq $v0,$a3,$v0
ret $zero,($ra)
_OtsRemainder64:
ldah $t12,h^_OtsDivData($zero)
lda $t12,l^_OtsDivData($t12)
negq $a1,$a2
cmovlt $a1,$a2,$a1
subq $a1,1,$t0
and $a1,$t0,$v0
sra $a0,63,$a3
negq $a0,$a2
cmovlt $a0,$a2,$a0
beq $v0,rl_pwr2
lda $at,-0x200($a1)
bgt $at,rl_lrgdiv
addq $a1,$a1,$v0
s8addq $v0,$t12,$t12
ldq $t0,0x8($t12)
ldq $a2,($t12)
umulh $a0,$t0,$v0
addq $v0,$a0,$v0
srl $v0,$a2,$v0
mulq $v0,$a1,$v0
subq $a0,$v0,$v0
xor $v0,$a3,$v0
subq $v0,$a3,$v0
ret $zero,($ra)
rl_pwr2:
subq $zero,$a0,$a2
cmovlt $a0,$a2,$a0
and $a0,$t0,$v0
beq $a1,divzer
xor $v0,$a3,$v0
subq $v0,$a3,$v0
ret $zero,($ra)
rl_lrgdiv:
bsr $at,div64
xor $t0,$a3,$v0
subq $v0,$a3,$v0
ret $zero,($ra)
_OtsModulus64:
ldah $t12,h^_OtsDivData($zero)
lda $t12,l^_OtsDivData($t12)
negq $a1,$a2
cmovge $a1,$a1,$a2
subq $a2,1,$t0
beq $a1,divzer
and $a2,$t0,$v0
beq $v0,ml_p2
xor $a0,$a1,$at
clr $a3
cmovlt $at,$a1,$a3
and $a0,$a1,$at
mov $a2,$a1
negq $a0,$a2
cmovlt $a0,$a2,$a0
cmplt $at,$zero,$v0
sll $v0,63,$v0
bis $v0,$a3,$a3
bsr $at,div64
cmoveq $t0,$zero,$a3
addq $a3,$a3,$a2
subq $a3,1,$at
negq $t0,$v0
cmovlt $at,$t0,$v0
cmoveq $a2,$zero,$a3
addq $a3,$v0,$v0
ret $zero,($ra)
ml_p2:
cmovge $a1,$zero,$a1
and $a0,$t0,$t0
cmoveq $t0,$zero,$a1
addq $a1,$t0,$v0
ret $zero,($ra)
nop
_OtsDivide64Unsigned:
ldah $t12,h^_OtsDivData($zero)
lda $t12,l^_OtsDivData($t12)
lda $at,-0x200($a1)
blt $a1,dul_big
addq $a1,$a1,$a2
srl $a0,33,$a3
beq $a1,divzer
s8addq $a2,$t12,$a2
bgt $at,dul_lrgdiv
cmpule $a1,$a0,$v0
bne $a3,dul_64bit
ldq $t12,($a2)
beq $v0,dul_end
blt $t12,dul_smpwr2
umulh $a0,$t12,$v0
ret $zero,($ra)
nop
dul_64bit:
ldq $t0,0x8($a2)
ldq $t12,($a2)
beq $v0,dul_end
beq $t0,dul_smpwr2
umulh $a0,$t0,$v0
zap $a0,0x0f,$a2
zapnot $a0,0x0f,$a0
srl $a2,$t12,$a2
addq $v0,$a0,$v0
srl $v0,$t12,$v0
addq $v0,$a2,$v0
ret $zero,($ra)
dul_smpwr2:
srl $a0,$t12,$v0
dul_end:
ret $zero,($ra)
dul_lrgdiv:
bsr $at,div64
ret $zero,($ra)
dul_big:
cmpule $a1,$a0,$v0
ret $zero,($ra)
_OtsRemainder64Unsigned:
ldah $t12,h^_OtsDivData($zero)
lda $t12,l^_OtsDivData($t12)
lda $at,-0x200($a1)
subq $a1,1,$t0
blt $a1,rul_big
and $a1,$t0,$a2
bgt $at,rul_lrgdiv
addq $a1,$a1,$v0
beq $a2,rul_pwr2
s8addq $v0,$t12,$t12
ldq $t0,0x8($t12)
cmpult $a0,$a1,$a2
bne $a2,rul_lss
ldq $a3,($t12)
umulh $a0,$t0,$v0
blt $a0,rul_carry
addq $v0,$a0,$v0
srl $v0,$a3,$v0
mulq $v0,$a1,$v0
subq $a0,$v0,$v0
ret $zero,($ra)
rul_carry:
zap $a0,0x0f,$a2
zapnot $a0,0x0f,$t0
srl $a2,$a3,$a2
addq $v0,$t0,$v0
srl $v0,$a3,$v0
addq $v0,$a2,$v0
mulq $v0,$a1,$v0
subq $a0,$v0,$v0
ret $zero,($ra)
rul_pwr2:
beq $a1,divzer
and $a0,$t0,$v0
ret $zero,($ra)
rul_lss:
mov $a0,$v0
ret $zero,($ra)
rul_big:
cmpult $a0,$a1,$t0
subq $a0,$a1,$v0
cmovne $t0,$a0,$v0
ret $zero,($ra)
nop
rul_lrgdiv:
bsr $at,div64
mov $t0,$v0
ret $zero,($ra)
divzer:
mov 0xfffffffe,$a0
clr $v0
clr $t0
call_pal 0x000000aa // PAL_gentrap
ret $zero,($ra)
.new_section .pdata, "dr4"
// 0000 Procedure descriptor for .text
.long .text // BeginAddress : 0
.long .text+0x7e4 // EndAddress : 2020
.long 00000000 // ExceptionHandler : 0
.long 00000000 // HandlerData : 0
.long .text+0x724 // PrologEnd : 1828
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