ser0.h

TDK 6521 SOC 芯片 DEMO程序

/***************************************************************************
 * This code and information is provided "as is" without warranty of any   *
 * kind, either expressed or implied, including but not limited to the     *
 * implied warranties of merchantability and/or fitness for a particular   *
 * purpose.                                                                *
 *                                                                         *
 * Copyright (C) 2005 Teridian Semiconductor Corp. All Rights Reserved.    *
 ***************************************************************************/
//**************************************************************************
//    
//  DESCRIPTION: 71M651x POWER METER - API for SERIAL Ports.
// 
//  AUTHOR:  RGV
//
//  HISTORY: See end of file
//
//**************************************************************************
//               
// File: SER0.H
//               
//**************************************************************************
//  Hardware access layer for UART 0
//  This defines two interfaces.  There's a specific interface, indexed
//  to uart 0.  There's also a generic interface, unindexed.  The idea
//  is that a protocol layer can be written in terms of the generic
//  interface, and then quickly ported to any serial interface just by
//  changing the include file, say from ser0.h to ser1.h
//

#ifndef SER0_H
#define SER0_H 1
#include "ser.h"  // definitions shared by all the uarts

// higher-level serial code is invoked by SER0_XMIT_INT and SER0_RCV_INT
// as defined in options.h

// Get data from the receive register; This can't be a macro, alas,
// because it has to clear the RI bit before it returns a value.
extern bool ser0_error;  // status for the most recent byte read
extern uint8_t ser0_rcv (void) small reentrant; /* define a common routine to find parity */
#undef ser_rcv
#define ser_rcv() ser0_rcv()

// Put data in the transmit register
#if SEVEN_BIT_0
#if PARITY_NONE_0               
// seven bits, no parity, two stop bits
#define ser0_xmit(_in_) \
    TI = 0; \
    SBUF = _in_ | 0x80  /* bit 7 is used as a second stop bit */ 
#else
// seven bits, even or odd parity, one stop bit
#define ser0_xmit(_in_) \
    TI = 0; \
    A = _in_ & 0x7F; \
    if (0 != (P ^ PARITY_ODD_0)) \
       A |= 0x80; \
    SBUF = A;
#endif
#else
#if PARITY_NONE_0          
// eight bits, no parity, one stop bit
#define ser0_xmit(_in_) \
    TI = 0; \
    SBUF = _in_
#else
// eight bits, even or odd parity, one stop bit
#define ser0_xmit(_in_) \
    TI = 0; \
    A = _in_;                /* Force correct parity flag. */ \
    TB8 = P ^ PARITY_ODD_0;  /* set parity */ \
    SBUF = A
#endif
#endif
// provide a macro so higher level driver code can run on either port
#undef ser_xmit
#define ser_xmit(_in_) ser0_xmit(_in_)

// Is the receive register ready?
#define ser0_rcv_rdy() RI
// provide a macro so higher level driver code can run on either port
#undef ser_rcv_rdy
#define ser_rcv_rdy() ser0_rcv_rdy()

// Does the receive register have an error?
#if PARITY_NONE_0               
// if no parity, there's no way to tell, so there's never an error
#define ser0_rcv_err() FALSE
#define ser0_clr_err()
#else
// if parity, publish the bit set by ser_rcv();
#define ser0_rcv_err() ser0_error
#define ser0_clr_err() ser0_error = FALSE
#endif
// provide macros so higher level driver code can run on either port
#undef ser_rcv_err
#undef ser_clr_err
#define ser_rcv_err() ser0_rcv_err()
#define ser_clr_err() ser0_clr_err()

// Is the transmit register empty?
#define ser0_xmit_rdy() TI
// provide a macro so higher level driver code can run on either port
#undef ser_xmit_rdy
#define ser_xmit_rdy() ser0_xmit_rdy()

// Enable an interrupt when the receive register ready.
#define ser0_enable_rcv_rdy() ES0 = 1;  REN = 1
// provide a macro so higher level driver code can run on either port
#undef ser_enable_rcv_rdy
#define ser_enable_rcv_rdy() ser0_enable_rcv_rdy()

// Disable an interrupt when the receive register ready.
#define ser0_disable_rcv_rdy() REN = 0
// provide a macro so higher level driver code can run on either port
#undef ser_disable_rcv_rdy
#define ser_disable_rcv_rdy() ser0_disable_rcv_rdy()

// Enable an interrupt when the receive register ready.
#define ser0_enable_xmit_rdy() ES0 = 1; TI = 1
// provide a macro so higher level driver code can run on either port
#undef ser_enable_xmit_rdy
#define ser_enable_xmit_rdy() ser0_enable_xmit_rdy()

// Disable an interrupt when the receive register ready.
#define ser0_disable_xmit_rdy() TI = 0
// provide a macro so higher level driver code can run on either port
#undef ser_disable_xmit_rdy
#define ser_disable_xmit_rdy() ser0_disable_xmit_rdy()

// Turn on the transmitter
#define ser0_xmit_on() /* should enable output, does nothing for serial 0 */
// provide a macro so higher level driver code can run on either port
#undef ser_xmit_on
#define ser_xmit_on() /* does nothing for serial 0 */

// turn off the transmitter
#define ser0_xmit_off() /* should disable output */
// provide a macro so higher level driver code can run on either port
#undef ser_xmit_off
#define ser_xmit_off() /* does nothing for serial 0 */

// permit other uses of the serial transmitter's pin
#define ser0_xmit_free() /* free the transmitter */
// provide a macro so higher level driver code can run on either port
#undef ser_xmit_free
#define ser_xmit_free() /* does nothing for serial 0 */

// Initialize UART 0
extern void ser0_initialize (enum SERIAL_SPD speed) small reentrant;
// provide a macro so higher level driver code can run on either port
#define ser_initialize(x) ser0_initialize(x)

#undef BAUD
#define BAUD BAUD_0

/***************************************************************************
 * $Log: ser0.h,v $
 * Revision 1.20  2006/09/27 00:57:01  tvander
 * More comments
 *
 * Revision 1.19  2006/09/09 01:10:00  gmikef
 * *** empty log message ***
 *
 * Revision 1.18  2006/08/09 00:56:36  tvander
 * *** empty log message ***
 *
 * Revision 1.17  2006/07/07 00:56:57  tvander
 * Made the serial initialization routines reentrant.
 *
 * Revision 1.15  2005/09/22 23:45:07  tvander
 * Clean build all models and unit tests, updated copyright to be fore Teridian
 *
 * Revision 1.14  2005/09/11 00:33:59  tvander
 * Clean compiles
 *
 * Revision 1.13  2005/09/07 05:28:05  tvander
 * 7 bit transmit wasn't managing the transmit interrupt flag!! (e.g. TI in uart0)
 *
 * Revision 1.12  2005/08/31 05:54:20  gmikef
 * First version w/ LAPIE interface.
 *
 * Revision 1.11  2005/08/28 02:15:12  gmikef
 * *** empty log message ***
 *
 * Revision 1.10  2005/08/19 01:04:39  gmikef
 * *** empty log message ***
 *
 * Revision 1.9  2005/05/19 00:31:01  tvander
 * Fixed so ser0 and ser1 can coexist in the same file. as they were designed to do.
 *
 * Revision 1.8  2005/04/21 02:00:26  gmikef
 * *** empty log message ***
 *
 * Revision 1.7  2005/04/09 02:04:26  gmikef
 * *** empty log message ***
 *
 * Revision 1.7  2005/04/06 23:04:43  tvander
 * First valid compile of flag
 *
 * Revision 1.6  2005/03/31 00:18:22  tvander
 * Minimally unit tested.
 * UART 0 is tested at 9600 BAUD 7 bits even parity, one stop bit.
 * UART 1 is tested at 300 BAUD 7 bits even parity, one stop bit.
 *
 * Revision 1.5  2005/03/24 22:12:51  tvander
 * Misc improvements
 *
 * Revision 1.4  2005/03/24 01:38:59  tvander
 * First successful compile of serial unit test
 *
 * Revision 1.3  2005/03/23 19:19:31  tvander
 * Added untested timer functions.
 * Updated iicdio and iiceep to reflect improvements in 6510 code.
 * ser0 and ser1 updated to provide features for flag.
 *
 * Revision 1.2  2005/03/15 00:32:35  tvander
 * More realistic hardware abstraction layer.
 *
 * Revision 1.1  2005/03/11 22:17:22  tvander
 * Structure
 *
 *
 * Copyright (C) 2005 Teridian Semiconductor Corp. All Rights Reserved.    *
 * this program is fully protected by the United States copyright          *
 * laws and is the property of Teridian Semiconductor Corporation.         *
 ***************************************************************************/

#endif